Does insulation tape block cross coupling?

[AQUAMAN]

I have a circuit add on to a gate driver of a high power IGBT

During the dV/dt of the collector-emitter, I get huge interference in my measurement circuit.

Do you think that insulation tape covering the power terminal would block the coupling to the measurement circuit? (see pic)

[tggzzz]

Do you think that insulation tape covering the power terminal would block the coupling to the measurement circuit? (see pic)

No: interference is caused by

• capacitance between conductors (i.e. wires or inside components themselves)
• inductance of conductors
• magnetic coupling
• leakage between conductors
• resistance of conductors

The last two are unlikely to be a problem, unless you have done something really stupid. Magnetic coupling might be an issue with high currents. My bet is on the first two.

You should think about the "parasitic" capacitance and inductance, and how to minimise them. Do some back-of-the-envelope calculations.

What's the picture without your added circuit?

[AQUAMAN]

My circuit is here

The memory capacitor C1 is what is being disturbed by dV/dt

There is either capacitive coupling from the gate path, or there is interference from the silver terminal (power terminal with high dV/dt) into my measurement circuit (the hand made PCB). The dV/dt in the gate path is however about 100x less than on that silver terminal and is in itself a result of the dV/dt on the silver terminal (but its coming through the chips inside module itself)

There is always crosstalk into the gate voltage when you get dV/dt on the collector emitter.

What I am wondering is whether I in effect have 2 tracks in parallel with the silver terminal and my PCB, and whether if in theory you could place insulation tape between tracks whether it would remove coupling. If I remember correctly the circuit I put on there with the insulation tape didnt suffer so much from this dV/dt disturbance and I am trying to work out why.

[tggzzz]

My circuit is here

Yes, but I don't think you've included the parasitics in your simulated circuit!

If I remember correctly the circuit I put on there with the insulation tape didnt suffer so much from this dV/dt disturbance and I am trying to work out why.

Don't come to us with partial information, especially incorrect partial information. You will waste our time and we will give irrelevant advice.

You note there is oscillation on the scope trace. Work out its frequency, then use 2*pi*f=1/sqrt(LC) to get some idea of the L and C involved. For example, consider a 20pF scope probe with a 150mm ground lead with L~=0.7nH/mm. That will self-resonate at ~100MHz

[AQUAMAN]

In another circuit I have included a much more detailed module model and a lot of parasitics

The only way I can get something similar to what happens in real life (the memory cap being disturbed and its level changed by dV/dt) is to place a 0.1pF cap between the collecter and the memory cap.

[tggzzz]

In another circuit I have included a much more detailed module model and a lot of parasitics

The only way I can get something similar to what happens in real life (the memory cap being disturbed and its level changed by dV/dt) is to place a 0.1pF cap between the collecter and the memory cap.

What's the frequency of the oscillation?
What's the length of the wires (and hence inductance)?
What's the capacitance?
Numbers, not adjectives.
Any correlation between the numbers, possibly as I indicated before?

[David Hess]

Just so I have the right idea, you are measuring the gate current and storing the peak in C1?

Electrostatic shielding can be used to block capacitive coupling.  Insulation will just raise the dielectric constant and make it worse.

Is the coupling from all of your probes causing more problems?