To just sum up the answers to my orginal point in the question, you're saying that these power on spikes do present a serious enough hazard to the longevity of chips to be worth worrying about in most designs one may produce. And that solving them can be as simple as adding some extra MLCC caps but having these be in series with some resistors before they go to the power rails, hence faking the properties of a high ESR electrolytic cap whilst still having the form factor and longer lifetime of a ceramic?
The image below is NOT the right circuit, but finding some generic series and parallel diagrams looked the best way to state more clearly than in words what I meant by that last sentence:
https://electricalacademia.com/wp-content/uploads/2017/10/Figure-3-Series-Parallel-Circuit-2.gifConsider only the circuit on the left
Ignore the absurdly high voltage battery, replace it with a low resistance power supply of Vcc, and with some amount of inductance in the wires from it to the area near the caps and chips
"R1" is where the existing MLCC caps in a circuit design are
"R2" would be a resistor of few ohms
"R3" would be some new extra MLCC caps
and the power rails towards the chip ofcourse would branch off from either end of "R1".
I'm guessing for 10uF to 100uF of MLCC's to compensate for you'd be looking a similar amount of MLCC's in series combinations, and if you had to put these a fair few cm away near the edge of an existing board design the trace lengths from them to the main MLCC's near the chips wouldn;t be long enough to cause more inductance sisues, plus they'd slow the rise of the power rails anyway so a sharp step wuld never reach the chip's deocupling MLCCs to cause any spiking.