Dipping my toe in digital electronics

[Martian Tech]

For the 6809 project, however, I have a slightly better plan: I just ordered two old Sony Watchman handheld TVs, and plan to try modifying them ala the TV Typewriter. For the 6809 this seems like the perfect display device, especially if I can get my hands on an MC6850 (or similar) to generate the video signal. If you bypass the receiver stage you can get pretty good resolution out of a black-and-white TV.

I think you mean 6845 - the 6850 is a serial controller.  You can find 6845s here: https://www.electronicsurplus.com/search/6845
They do also have 6850s available, should you need those.  I've had good luck with parts from this vendor.

Another option on the video is to use the techniques from Don Lancaster's Cheap Video Cookbook: https://www.tinaja.com/ebooks/cvcb1.pdf
but you lose some of your address space with that...

[jdutky]

If you have a 74LS00 Quad NAND Gate, you can replace the oscillator with a debounced pushbutton.  Then you can walk the flops through the 4 states one step at a time.

Document page 10..11 "Hardware Debouncers"

https://my.eng.utah.edu/~cs5780/debouncing.pdf

Those open triangle symbols are the Vcc rail for the pull-up resistors.

Yes, I did that (but I used a 74LS14 instead of the 74LS00), and saw that the Q and ~Q outputs changed on different parts of the clock signal (Q on the falling edge and ~Q on the rising edge), which is not what I expected.

I don't think that's the issue with my circuit, but I'm not willing to rule anything out at this moment.

[jdutky]

I didn't spend a lot of time with it but your schematic does not appear to match your wiring diagram.  The circuit you show wired up has the inversion and I suspect it would provide the 90 degree shift /4.   

https://www.eevblog.com/forum/microcontrollers/typical-speed-of-fpgas/msg1279898/#msg1279898

Damn it, you are right. That means that I'm just reproducing the circuit from the datasheet, only upside down (or backwards?).

I've been looking at doing this with two D FFs (74LS74), as that looks easier to understand (to me), and adding a 74LS14 afterwards to clean up the outputs.

The problem with just building the circuits given in a datasheet is that you (that is "I') don't actually understand how the circuit works when you are most likely to have made a mistake implementing it and need to be able to debug it. I feel like I'm slowly understanding how this circuit is supposed to work.

[joeqsmith]

...
I've been looking at doing this with two D FFs (74LS74), as that looks easier to understand (to me), and adding a 74LS14 afterwards to clean up the outputs.

The problem with just building the circuits given in a datasheet is that you (that is "I') don't actually understand how the circuit works when you are most likely to have made a mistake implementing it and need to be able to debug it. I feel like I'm slowly understanding how this circuit is supposed to work.

While the simulation may help you along with a good book the most important thing is not to get discouraged and just keep plugging away at it.   

Consider splitting the circuit in half using a single DFF.   If you tie Q to D and say it all resets to 0 so Q starts out 0.  So you clock a 0 into D and Q goes to 0 which feeds back to D. We clock in another 0.  On and on it goes, doing nothing.

If we instead use Q' as the feedback to D, Q' resets to a 1.  The first cycle, we clock a 1 into D which will cause Q' to go to a 0.   The next cycle, we clock a 0 into D and Q' returns to a 1.   So the circuit toggles or changes state every clock, basically dividing the clock by 2.   

Your 6809 need 4 states to get that 90deg.  So you need to divide by 2 again.    You could take the Q from that first D and use it to clock a second D that uses the same Q' feedback.  Two dividers in series is a divide by 4.   Maybe then use one clock to drive both D FFs and use one feedback path like I show from the second FF's Q' to the first FF's D.   Get through that and ask yourself, why would you use one method over the other....

[RJSV]

rstofer mentioned that Ben Eater has posted some great stuff, for signal level. I especially interested in the state machine / micro-processor responsible for control.

[rstofer]

rstofer mentioned that Ben Eater has posted some great stuff, for signal level. I especially interested in the state machine / micro-processor responsible for control.

State machines are everything!  Ben Ester is doing a form of microcode in Video 1.  I didn't watch the rest of the series.

https://eater.net/8bit/control

Microcode is an organized way of implementing a state machine.  Each microcode state makes decisions on the next state as well as outputting control signals that will be in effect when the next clock comes along.  Things like "Load Accumulator" are output from a bit in the microcode and enable the accumulator flops to get loaded from the bus on the next clock.

Microcoding was introduced on the IBM 360 and the 8" floppy was invented by IBM to boot load the microcode.  This approach allowed sophisticated users to alter the microcode to create different instructions.  Not that IBM approved of this practice.

The other way to build the control is with some form of Hardware Description Language (HDL) for an FPGA or ASIC.  The HDL will read like computer code and be relatively clear in what happens at each state.  Microcode is a lot more difficult to decipher unless the author documented each step.  Imagine a microcode word of 100 bits wide (or more).  It is broken up into fields and each field is assigned a default value for the states where it isn't relevant but, in the end, you, as the programmer, have to manipulate all 100 bits times as many words as are required for the entire processor.  There is a tool known as a 'meta assembler' that is used to create the bit pattern from a source 'language'.  Cool stuff!

If you really want to know this stuff there are two approaches:  First, follow along with Ben Eater's approach and discrete chips or get with the FPGA program right out of the gate.  Trust me, changing a line of code is a lot easier than rewiring a breadboard.

Curl up with this document (LC3 Appendix C) and see how a machine is designed.  At least one approach.  There is a hardware diagram, a state machine diagram and a list of signals to create.  These signals control the various pieces of hardware.  On the last page, there is a form for creating the microcode as this machine, as given, is microcoded.  Mine is written in VHDL.  Just because I like microcode, I may eventually recreate it.  It would be a much smaller project because all of the decision making is done by the microcode creator.  It would be a fun project!

http://people.cs.georgetown.edu/~squier/Teaching/HardwareFundamentals/LC3-trunk/docs/LC3-uArch-PPappendC.pdf

[tggzzz]

Microcode was invented in 1951.

Alsohava a look ath the Research Machines Orion 1,which used the 2900 series and where the microcode was under user control.

[jdutky]

...
I've been looking at doing this with two D FFs (74LS74), as that looks easier to understand (to me), and adding a 74LS14 afterwards to clean up the outputs.

The problem with just building the circuits given in a datasheet is that you (that is "I') don't actually understand how the circuit works when you are most likely to have made a mistake implementing it and need to be able to debug it. I feel like I'm slowly understanding how this circuit is supposed to work.

While the simulation may help you along with a good book the most important thing is not to get discouraged and just keep plugging away at it.   

Consider splitting the circuit in half using a single DFF.   If you tie Q to D and say it all resets to 0 so Q starts out 0.  So you clock a 0 into D and Q goes to 0 which feeds back to D. We clock in another 0.  On and on it goes, doing nothing.

If we instead use Q' as the feedback to D, Q' resets to a 1.  The first cycle, we clock a 1 into D which will cause Q' to go to a 0.   The next cycle, we clock a 0 into D and Q' returns to a 1.   So the circuit toggles or changes state every clock, basically dividing the clock by 2.   

Your 6809 need 4 states to get that 90deg.  So you need to divide by 2 again.    You could take the Q from that first D and use it to clock a second D that uses the same Q' feedback.  Two dividers in series is a divide by 4.   Maybe then use one clock to drive both D FFs and use one feedback path like I show from the second FF's Q' to the first FF's D.   Get through that and ask yourself, why would you use one method over the other....

This is exactly what I was thinking, and that you could tap off the Q or ~Q of different flip flops to get wave forms with the right phase and polarity. I realize that this is what the circuit given in the datasheet is doing, but it just seems clearer to have one flip flop per phase. It's certainly cheaper to do it all in one DIP, but as I have said before, expense (within reason) is not a driving concern.

My paper simulation built a clock circuit with 4 DFFs in series, all clocked by the same input, with the ~Q of one FF fed to the D of the next, then wrapped from the last DFF back to the first. I envision this as a bucket line passing the rising edge down the line on each pulse (falling edges, so div by 2). At each DFF you can tap off Q or ~Q to get a clock signal at a particular phase. Then it became obvious that I only really needed two FFs to do the whole job, one for a 90 degree div by 2 clock, and the other for a 180 degree div by 2 clock with two polarities.

I can fit this easily into a 74x74, but if I did it in a 74LS175 (quad D FF) then the clock signal going to each FF is internal to the package, which might reduce some of my pain points on the bread board build. I just happen to have a couple of 74LS175 lying around.

[joeqsmith]

...
My paper simulation built a clock circuit with 4 DFFs in series, all clocked by the same input, with the ~Q of one FF fed to the D of the next, then wrapped from the last DFF back to the first. I envision this as a bucket line passing the rising edge down the line on each pulse (falling edges, so div by 2). At each DFF you can tap off Q or ~Q to get a clock signal at a particular phase. Then it became obvious that I only really needed two FFs to do the whole job, one for a 90 degree div by 2 clock, and the other for a 180 degree div by 2 clock with two polarities.
...

For what you want to do, I think the two DFF in a single DIP is all you need, just like I show in those previous circuits.  If you can get it working with the parts you have on hand, all the better.   

[jdutky]

I took a few days off, read a bunch of stuff, redrew the clock generator circuit from yet another version of the datasheet (the Hitachi datasheet for the HD6809E), and rebuilt the circuit on a different breadboard. Well, either my old circuit was flawed, or the old breadboard was faulty (or both. It's entirely possible that both are true), but the new circuit on the new breadboard works perfectly!

I went directly from there to hooking up the 68B09E, hard-wiring a NOP (hex 12) on the data bus, wiring some LEDs to the upper address lines, and connecting a nicely debounced push-button to the RESET pin, I have managed to get the CPU to run its first program! (as evidenced by the uppermost three address line visibly flashing)

I'm so excited that it's just silly. Thanks to everyone (especially joeqsmith) for your advice and encouragement. This is such a great community, and I'm having so much fun.

attached are my notes with the redrawn schematic and circuit plan, the full circuit (with inverter and CPU), and the scope trace of the improved clock output (I think that's the E_cpu output, but it might be Q). Next stop, hooking up RAM, ROM, and a peripheral interface adapter (or two) for some switches and lights.

[joeqsmith]

Perseverance seems likes becoming more rare.  Good job sticking with it.  Congratulations getting something running.   Time to add some ROM and RAM...   

[jdutky]

Perseverance seems likes becoming more rare.  Good job sticking with it.  Congratulations getting something running.   Time to add some ROM and RAM...   

That's the plan (I wanted to use a 68B50 ACIA, but the 85C30 is so much more capable, and easier to obtain).

Also, time for flippenswitches and blinkenlights.

[joeqsmith]

I had a friend with a Radio Shack color computer.  He bought the modem for it.  From what I remember, they did not use a UART but rather bit banged the port in tight loop.  Considering that most modems were 300 BAUD back then, they decided to save some cost. 

[jdutky]

I had a friend with a Radio Shack color computer.  He bought the modem for it.  From what I remember, they did not use a UART but rather bit banged the port in tight loop.  Considering that most modems were 300 BAUD back then, they decided to save some cost. 

A tight look sounds absurdly wasteful, but I recall other, far more expensive and resource rich systems of the same period doing similar things. It boggles the mind. You've got several thousand instructions per bit at 300 baud, would it have broken the bank to have a 600 Hz interrupt and sample the serial line in the interrupt handler?

I'm reading through The Cheap Video Cookbook getting ideas for how to drive a video display, and it also seems absurdly wasteful. I've also got a PDF of Son of Cheap Video, which seems much less wasteful. Still, I have the kinds of resources that people only dreamt of in the early 80s: I'll probably just throw an entire 8KB SRAM at any video system I build, and have the CPU copy data in during the vertical blanking interval.

I really enjoyed Ben Eater's World's Worst Video Card lesson

[tggzzz]

That's the plan (I wanted to use a 68B50 ACIA, but the 85C30 is so much more capable, and easier to obtain).

When mixing processor families, be very careful that setup and hold times are observed. That can be non-trivial given the different "styles" of interface control signal.

I discovered such a problem in somebody else's design, but since that was <1985, I've forgotten the details.

[joeqsmith]

I had a friend with a Radio Shack color computer.  He bought the modem for it.  From what I remember, they did not use a UART but rather bit banged the port in tight loop.  Considering that most modems were 300 BAUD back then, they decided to save some cost. 

A tight look sounds absurdly wasteful, but I recall other, far more expensive and resource rich systems of the same period doing similar things. It boggles the mind. You've got several thousand instructions per bit at 300 baud, would it have broken the bank to have a 600 Hz interrupt and sample the serial line in the interrupt handler?

I'm reading through The Cheap Video Cookbook getting ideas for how to drive a video display, and it also seems absurdly wasteful. I've also got a PDF of Son of Cheap Video, which seems much less wasteful. Still, I have the kinds of resources that people only dreamt of in the early 80s: I'll probably just throw an entire 8KB SRAM at any video system I build, and have the CPU copy data in during the vertical blanking interval.

I really enjoyed Ben Eater's World's Worst Video Card lesson

I used to have all the technical manuals for the Radio Shack color computer and they had a warning about using PEEK and POKE in certain areas.   It seems they did not fully decode the bus and you could end up with contention, which they claimed could damage the computer.   

[Martian Tech]

When mixing processor families, be very careful that setup and hold times are observed. That can be non-trivial given the different "styles" of interface control signal.

True dat.  I interfaces an 8253 to a 6809 just because I had an old 8253 in a ceramic package and thought it would be cool to use it instead of trying to track down a 6840.  Ended up having to add a 74LS31 to get it to work...

[joeqsmith]

Not sure if this would be of any interest to the OP.   

https://jbevren.wordpress.com/2018/09/22/designing-a-6809-sbc/ 

[jdutky]

Now that I have a working clock generator I think I'm ready to put together a simple SBC with the 6809. I've got a handful of parts that I expect to put together as a basic computer:

• The 68B09E CPU
• One 6264 8Kx8 SRAM
• One 28C64 8Kx8 EEPROM
• One 68B21 PIA
• One 74LS76 dual JK FF (clock gen)
• One 74LS04 hex inverter (clock gen+misc)
• One 74LS138 3-8 DMUX (chip selection)
• One 8.0MHz full-can crystal oscillator
• several switches and LEDs as basic UI
• assorted capacitors, resistors, and diodes for bypass, current limit, and debounce
• something to give me +5V and Ground on the board
• one 30mm x 50mm prototype board

I'm looking over the pinouts for the SRAM, EEPROM, CPU, and PIA and I am a bit mystified by something: I had expected to wire the clock up to every major chip on the board, especially the memory chips, but neither the SRAM nor the EEPROM appear to have a clock input. Only the CPU and PIA have clearly labeled clock pins (Q and E on the CPU, and E on the PIA). How does this work? Do the memory chips just not care about the system clock?

I'm guessing that I will wire the R/W line from the ~OE and ~WE lines of the SRAM, with one of them getting the R/W signal inverted (it's a good thing I have that 74LS04 in the mix), then wire one of the outputs from the DMUX to one of the CS lines (and the other can be tied high or low as appropriate) and that will be enough to make the chip active when the CPU does reads and writes in it's assigned address range and make it sample the address and data busses at the right times. This, of course, is just a guess based on what I think I've understood from the datasheets and various things on the interwebs.

Not that I don't value the thrill of learning by trial and error, but am I understanding how this will work, or am I about to experience a pitfall for novices?

[Electro Fan]

It is fascinating to see a guy know about half of what it takes to build a computer a semiconductor, logic gate, and pin at a time - which is very impressive, while watching him figure out the other half as he goes - which is equally or more impressive.  jdutky you are an excellent role model. 

[jdutky]

It is fascinating to see a guy know about half of what it takes to build a computer a semiconductor, logic gate, and pin at a time - which is very impressive, while watching him figure out the other half as he goes - which is equally or more impressive.  jdutky you are an excellent role model. 

I was going to be an EE, way back in college, but then I bailed for CS, so it's almost literally true that know exactly half of what I need to know for this: everything up to the end of sophomore year, in fact.

[Electro Fan]

It is fascinating to see a guy know about half of what it takes to build a computer a semiconductor, logic gate, and pin at a time - which is very impressive, while watching him figure out the other half as he goes - which is equally or more impressive.  jdutky you are an excellent role model. 

I was going to be an EE, way back in college, but then I bailed for CS, so it's almost literally true that know exactly half of what I need to know for this: everything up to the end of sophomore year, in fact.

It might have been your sophomore year but I have a hunch that not everyone was paying attention and assimilating the material as well as you.  You really are inspirational in your ability to synthesize the glue logic of CS on top of EE.   

[jdutky]

I was going to be an EE, way back in college, but then I bailed for CS, so it's almost literally true that know exactly half of what I need to know for this: everything up to the end of sophomore year, in fact.

It might have been your sophomore year but I have a hunch that not everyone was paying attention and assimilating the material as well as you.  You really are inspirational in your ability to synthesize the glue logic of CS on top of EE.   

Oh, I assure you that I was quite the bobblehead in my college years, though I was doing well enough in my physics and engineering classes to score in the top 10-15% (so, yes, there were people who were paying much less attention than I was, but I was never #1 in the class. Someone once said that if you're the smartest person in the room then you're in the wrong room, and I was never in the wrong room). In the intervening decades, however, I have made some progress in both determination and perspicacity. The pandemic, however, has given me copious extra time to pursue interests outside of my professional career, and electronics was always something that fascinated me, so it's easy to concentrate on.

When I was in college, still thinking I was going to be an engineer, I took a Fortran programming class. In the class with me was an older engineer who was taking the class for professional development, and he had the rockiest start to the semester that I have ever seen. It turns out that it took him almost a month to figure out that each instruction in the program happened in strict sequential order, rather than all-at-once (as in an electrical circuit). The way his high degree of technical training utterly betrayed him in a relatively elementary course made a huge impression on me, not as a source of mirth or derision, but as a cautionary tale to never let what you know get in the way of what what you want to know.