So I've made some progress on the clock generator circuit, first we have the circuit that I'm actually trying to build (from the MC68B09E datasheet), and the breadboard I've put together to implement it (the chips are, clockwise from upper left: 74LS74 dual D-type flip-flops, 74LS04 hex inverters, 74LS76 dual JK flip-flops, and a 74S51 standing in for the 74LS10 3-input NAND while I'm waiting on a purchase to arrive. On the right hand side you can see my improved probe discipline to sample the output Q and E signals. So long as I don't make any sudden moves, or breath, the probes will sit nicely in the breadboard sockets and let me take pictures. The tactile switch in the upper right allows me to trigger the MRDY input). Next we have several pictures of the oscilloscope display showing 1) the clock sampled at the oscillator's output, 2) the clock sampled where at the 74LS76 clock inputs, and 3) the Q and E output signals.
Clearly something is terribly wrong, I suspect that it is a problem with how I have wired the circuit together, but I'm not entirely sure of that. The factors that suggest that I have mis-wired the circuit are that the Q high time is much longer than the low time, and the fact that I repeatedly mis-wired the connections around JK flip-flops several times.
The scope settings are 200ns/div horizontal and 5V/div vertical. The oscillator is 3.088 MHz, though I'm planning to use an 8 MHz oscillator in the final version (I'm waiting on a purchase to arrive).
UPDATE: looking at it now, and at the two samples of the clock signal, I'll bet I could clean up the clock signals just by taking them all directly from the output of the oscillator, rather than doing a running line like that, but I don't think that the clock signal is the problem here because while it gets a little worse, it doesn't get bad enough to be confusing the logic gates. I think I've clearly got something wired wrong and am inducing an unstable state in the JK flip-flops. I dimly recall (from college courses) that this was a problem even with ideal logic circuits run in simple simulations.
UPDATE the 2nd: upon further reflection, it occurs to me that I have made this more complicated than it needs to be: I only need the "optional" portion of the circuit if I am going to support other bus masters in the system. I can omit the optional portion, lose two ICs (the two on the left) and get a circuit that is probably simple enough to debug at my current skill leve