Differential Pairs Wiggling - Done by hand

[pigtwo]

Hello everyone,

I'm working on a board that has four LVDS lines(8 wires in total) and I am trying to make the etch length equal for all of them.  I'm using OrCAD 16.3 and I don't have the delay tune functions or the ability to define differential pairs.  So I am doing it all by hand.  I'm just wondering how careful I need to be with the wiggles/spacing.  Attached is a picture of how I've done it so far. 

Should I focus on keeping the pairs close to each other like I do on the right side pairs, or should they mirror like I do on the far left side?  Or does it not really matter?

Also, how closely should I match the lengths?  Right now the max difference in length between any of the lines in 18 mils. 

The signals are video signals if that makes a difference. 

Sorry if this is kind of a vague question, I'm pretty new to PCB design and I'm trying to make sure there's no problems when I go to get it manufactured. 

Thank you!

[Godzil]

That wouldn't answer to your question, but you must have been really patient to do that! wow I'm impressed 

[wraper]

Actually all of this looks like a mess, why all of them are cramped in one pile? You shouldn't do any mirroring (obviously doesn't help to keep the right impedance) but exactly opposite.

[MagicSmoker]

....Attached is a picture of how I've done it so far. 

You're doing it wrong. Traces - including meanders - carrying differential signals need to be routed with a constant distance between them (and with as few layer transitions/vias as possible).

Also, how closely should I match the lengths?  Right now the max difference in length between any of the lines in 18 mils.

Length mismatch depends on the allowed timing skew multiplied by the propagation speed of the signal on the board which itself depends on the dielectric constant of the board material (typically 150-170mm/ns for a trace on the surface of an FR4 board, depending on thickness, exact dielectric constant - usually around 4.6, etc.). E.g. - you are allowed 100ps of skew between signals (not between the two traces of a differential pair!); 100ps = 0.1ns = ~15-17mm of total length mismatch (assuming no other components add to the total skew).

I'm pretty new to PCB design and I'm trying to make sure there's no problems when I go to get it manufactured.

LVDS signalling and new to PCB design? Oh boy...


[edit - expand on length mismatch]

[dom0]

    I'm pretty new to PCB design and I'm trying to make sure there's no problems when I go to get it manufactured.

You won't get it right the first time. Nobody does.

[pigtwo]

Thank you for all the advice.  I (painstakingly) redid the design so that the traces have a constant separation.  I still had to put in some little bumps to even it out at the end. 

It looks better now and hopefully it works. 

LVDS signalling and new to PCB design? Oh boy...

I know!  But this shouldn't be too bad because all it does is take the LVDS lines from one connector to another.

[wraper]

I know!  But this shouldn't be too bad because all it does is take the LVDS lines from one connector to another.

It IS bad if looking on the picture. IMO you have no clue what controlled impedance means.

[free_electron]

you are dealing wiht two problems

1) the length inside a pair. The _p and _n need to be tuned to match each other.

2) the length between the pairs.

To tune 1 pair : insert wigglies in the shortest trace.  the rule of thumb for the wigglies :
   - it should not pull more then double the clearance away.  more than that creates too large discontinuities in impedance.
   - the verticals must be 3 or 4 clearances away to avoid self-coupling.

  for example : a pair that looks like this : 4 mil trace , 6 mil gap , 4 mil trace.

Code: [Select]

              |<--18-->|<--18-->|<--18-->|       <= 3x track to track spacing. you can bump this to 4 times if you want.
               ________         _________
P: __________ /        \_______/         \_______
         6        12       6       12        6           <- no more than double track to track spacing when pulling away.
N: ____________________________________________


So for every 'wiggle' you add basically 2x the track to track space in length.


if you have adjacent pairs stagger the wiggles

Code: [Select]


good :
        ___     ___
   ____/   \___/   \_____________________
   ____________________________________

                        ___     ___
   ____________________/   \___/   \____
   ______________________________________

bad :

        ___     ___
   ____/   \___/   \_____________________
   ____________________________________
        ___     ___
   ____/   \___/   \_____________________
   ____________________________________



The wiggles should be inserted close to a terminating point. avoid having them in the middle of the run. reflecting signals could double-bounce keep time of flight as short as possible between the wiggles and the termination.

Spacing between coupled pairs must be 3 to 4 times the inter paid spacing.

so if you have a 4 lane bus ( like dvi ) set up as 4 mil track and 6 mil gap then the routing should look like theis

Code: [Select]


PCLK -----------------------
                      6                              <- intra pair spacing ( spacing in 1 pair )
NCLK -----------------------
                   18 to 24                     <- inter-pair spacing ( spacing between pairs )  = 3 to 4x intra pair spacing
PD0  ------------------------
                       6
ND0 ------------------------
                    18 to 24
PD1  ------------------------
                       6
ND1 ------------------------
                    18 to 24
PD2  ------------------------
                        6
ND2 ------------------------




[free_electron]

the same rule applies if you need to meander a pair : make sure the pair does not couple to itself. by keeping the gap at least 3x the pitch

[rsjsouza]

Excellent info, ASCII art... Bookmarked! Thanks for the information free_electron!

[MagicSmoker]

...
It IS bad if looking on the picture. IMO you have no clue what controlled impedance means.

LOL... the example you provided above isn't much better: the meanders are too close to each other.

Also, do try to keep in mind this is the beginner's section and thus the thread-starters are expected to be somewhat clueless. Those of us with more experience/knowledge should either post something helpful or not reply at all. It's a simple rule of behavior that has kept me out of many pointless arguments since I first found out about USENET in 1990.

you are dealing wiht two problems

1) the length inside a pair. The _p and _n need to be tuned to match each other.

2) the length between the pairs.

Yes, this is a more detailed explanation than what I gave and has some very useful rules of thumb in it. The only one I would quibble with somewhat is:

...
Spacing between coupled pairs must be 3 to 4 times the inter paid spacing.

Inter-pair spacing should be a minimum of 3x the intra-pair spacing - preferably 6x if space allows. - to prevent "signal feedthrough" (ie - bypassing the meanders completely).

[T3sl4co1l]

You're doing it wrong. Traces - including meanders - carrying differential signals need to be routed with a constant distance between them (and with as few layer transitions/vias as possible).

The importance of differential rules is extremely overstated.  The common or normal mode impedances are both lower (and necessarily so) than the differential (coupled) impedance, in any coplanar construction.

That means you're better off thinking of them as individual traces.

It matters very little that the traces actually be routed together, so long as they get there at the same time, both between traces in a pair, and between synchronized pairs.  (Unsynchronized pairs, such as PCIe or Ethernet, do not care about matching from pair to pair.  HDMI and others, I don't know; you'll have to check the standard, or ask someone else.)

The only reason it is at all important, is because, to obtain the benefit of differential signaling, both traces should be exposed to the same noise environment.  They should be routed symmetrically, and locally (at the same point in space and in trace length), over the same underlying traces, or over gaps/splits in power pours.

Signal quality is also generally overblown; commercial standards are intentionally quite robust.  Examples range from SSTL (a pseudo-differential signaling method used for desktop CPU to SDRAM and system chip communications), to PCIe, USB, SATA and other bus or cable oriented serial channels (which are differential and use preshoot, relatively high transmitter levels, and conservative thresholds, to account for noise and losses in the signal path).  Demanding signal quality applications are basically confined to special purpose or custom hardware: telecomms, timing and data processing instruments, etc.  In these cases, signal degradation has consequences for data integrity, bit errors, timing errors, jitter, and etc.

Tim

[pigtwo]

@free_electron Thank you for the detailed information.  That actually covers a few other things that I was confused about.  I'll have to bookmark this.

[pigtwo]

I'm just curious, is there a preferred way to pull away?  Should it pull away at and angle or just immediately pull away?  Attached is a picture showing an example of what I mean.   

[T3sl4co1l]

Smoother transitions are always better.

In reality, if the undulations are shorter (in trace length or physical length per cycle) than a fraction of the rise time, it doesn't matter in the slightest.  In fact, you can use that fact as a maximum constraint on how large and wide they should be.

Example: an LVDS signal with 500ps rise time (= 150 mm) should have such features smaller than, oh, 1/10th of that, or 15mm.  Which is a pretty big allowance, simultaneously on all of: 'hump' length and width, trace positioning and coupling, and length matching.

Incidentally, an undulation pattern exhibits a lowpass kind of characteristic, tending to reflect very high frequencies.  This is why the rise time matters; too large and those features would make the rise more sloppy (increased risetime, and perhaps ringing, depending on what filter characteristic the geometry yields).

As for magnitude of effect, you know what it looks like to gaze down a long chain of windows or mirrors?  It's that kind of effect, electrically, but because there is so little difference to the signals in this case, it's something like a hall of very thin, nearly invisible sheets of plastic film.  Each layer, each hump in the trace, has so little effect on the transmission, even after a hundred layers (humps), that your signal still gets through loud and sharp.

The nasty things to worry about are changes in trace width or dielectric thickness (say if the inner layer beneath the trace is missing in large areas), which act more like sheets of glass rather than thin films in my example.  The signal will still get through, but it doesn't take too many of those to block it off completely.

Tim