Development of 500Vpp Linear Amplifier

[Vovk_Z]

I made a first attempt to simulate the suggested circuit and extend it to a higher voltage by stacking mosfets. I had no luck simulating it with ngspice in a DC analysis. The result seems odd and the convergence is bad. Can you guys look into the schematic and tell me if the topology is correct so i can build a simple prototype?

How high do you want to go? What Vpp do you want? That circuit is quite simple and just works (possibly after adjusting source resistors for your needed output current and simple source current adjusting).
Here is one more circuit with this exact idea Class AB inverting amp uses two floating-amplifier cells. It can deliver about 1000 Vpp. The only drawback I remember - the more stacked Mosfets the slower it became (but still has >= 1-2 kHz bandwidth).

For a 100 mA output current, you need to use 10 R Source resistors (+-50%).

Pros and cons of those two ideas (Bootstrapping vs Floating-amplifier cells):
1) Floating-amplifier cells with N-Mosfets:
pros: uses only N-Mosfets which are easy to find. If something goes wrong you lose only MOSFETs and optocouplers. It can be considered quite reliable and repairable.
cons: it is slow, it works up to 1-10 kHz.  Source current depends on the heatsink temperature and may vary.
2) Bootstrapping:
pros: very fast. It can be almost as fast as used opamp itself.
cons: typically needs both N and P Mosfets (or NPN & PNP bipolar transistors), which are hard to find now (high voltage ones). If something goes wrong - you lose MOSFETs together with opamp (more loss).

I would use bootstrapping topology up to 200 Vpp, and Floating-amplifier cells topology for higher voltages (if slow speed is not a problem).

[magic]

There is one more topology which reduces HV electronics to absolute minimum.

I have used this topology before with good success. I haven't come across any source material on this (aside from being a favourite of SMU designers) - I would like to read into the background more. Does your image come from a book or article?

The image is from Edward Cherry's Electronics World article "Ironing out distortion, part 2", where it is only used to illustrate similarities between emitter follower and common emitter output stages. There is no discussion of complete amplifiers of this kind and the topology is unattractive for audio due to the multiple PSUs requirement.

I imagine the simplest complete amplifier would add Miller compensation around this output stage and an operational transconductance amplifier in front to drive it.

[langwadt]

There is one more topology which reduces HV electronics to absolute minimum.

I have used this topology before with good success. I haven't come across any source material on this (aside from being a favourite of SMU designers) - I would like to read into the background more. Does your image come from a book or article?

The image is from Edward Cherry's Electronics World article "Ironing out distortion, part 2", where it is only used to illustrate similarities between emitter follower and common emitter output stages. There is no discussion of complete amplifiers of this kind and the topology is unattractive for audio due to the multiple PSUs requirement.

I imagine the simplest complete amplifier would add Miller compensation around this output stage and an operational transconductance amplifier in front to drive it.

[macaba]

Thanks for the responses regarding the grounded output topology. From a browse of audio forums, this topology for audio usage seems to originate in 1982. As we all know, electronics doesn’t tend to have an outright best answer, it’s more about which compromises are acceptable to you. In my case, for my lab instrumentation build, I was happy to have the downside of per-channel transformer windings (with low pri-sec capacitance) in return for the reduced part count, low voltage frontend & speed.

It looks like this thread has hit all the major topologies so it will be interesting to see what OP goes with.

[magic]

For the record, this is what I meant by a simple, one chip solution for driving this grounded emitter power stage. Simulation seems to agree that it should work.

[David Hess]

For the record, this is what I meant by a simple, one chip solution for driving this grounded emitter power stage. Simulation seems to agree that it should work.

Besides massively exceeding the breakdown voltage of the output transistors, the open loop frequency response changes with operating point, so frequency compensation will be very difficult.

[GN89]

How high do you want to go? What Vpp do you want?

For the first attempt I'm happy with the 400Vpp but later versions might be higher. More bandwidth is always good for the use case because probe potential tracking is planned for this case. More important is more current in later versions up to 0.4A.

I tried simulation Leonid Ridico's design with ngspice but as soon as I add the negative rail there is no convergence at all. Maybe ngspice is not capable for simulating these circuits. I will try to build a prototype because mosfet stacking is easy as I showed in my previous design.

I had a look into the EDN atricle about boostrapped opamps. The problem I see is that I need a operational amplifier which is capable for that current. Let's say 15V supply voltage for the floating opamp which means 1.5W power dissipation. For later versions this would be even more. this could be solved by using a current buffer wich could be low voltage because all is floating.

The Transistors to let the opamp float should be stacked in that case to be operated in a safe area with that voltages.

[mawyatt]

If the load is allowed to be floating wrt to ground, a differential drive (H Bridge) can reduce the voltage levels across the output stages.

Best,

[magic]

the open loop frequency response changes with operating point, so frequency compensation will be very difficult.

One would need to build this to be 100% sure, but I don't see the problem. Miller compensation is easy and well behaved, output stage gain variation is hidden behind feedback through C1, the stage is a transimpedance amp with frequency response determined by that one capacitor. It only needs a certain minimum bias to maintain sufficient gain and bandwidth inside that local loop, and in this particular topology it only needs bias on either one of the two transistors at a time, because base voltage swings are applied to both transistors equally.

It simulates OK, also with steps to other voltages (and resulting load currents), including zero.

[GN89]

I made one simple version for a converter which uses the PA97 high voltage operational amplifier. The PA97 can provide 10mA which which is enough to drive an output buffer of stacked mosfets. I attached the schematic, transient, dc and ac simulation. This one simulates well up to 1kHz with driving a resistive load of 400 ohm.

What is missing is the gate protection diodes for the mosfets. Could somebody look into that if there is some possible optimization for a bit more bandwidth and if the PA97 needs more protection because that is the expensive part (about 150 USD).

[magic]

Blown FETs may result in blown chip, so it's a good idea to protect them. Problem is, overcurrent protection means limiting gate-source voltage to a few volts in the event of output short. Since we have no control over source voltage (it's shorted), the usual solutions sink current from the gate to source to reduce Vgs. Unfortunately, your PA97 will try to fight it and source more current into the gate until it blows up, because it has no overcurrent protection. You would need to increase your gate resistors orders of magnitude to get worst case output current under 10mA.

If I were desperate to really make it work with this opamp, I would try to add overcurrent protection to it by putting zeners on pins 4 and 6. But YMMV and it's 150 bucks down the drain if something goes wrong. Not even 100% sure if the schematic is complete and fully accurate.

[BrianHG]

You can try modeling and making your own bipolar op-amp, a simple one's design and function is illustrated here:

https://www.eevblog.com/forum/chat/the-history-of-the-invention-of-the-op-amp/msg5538773/#msg5538773

Use HV npn/pnp transistors to make this one.  The basic design illustrated makes up many simplistic audio amplifiers with +80v designs, so, I do not know how hot driving such a design with a ~ +/-260v rail will make the differential input and class A stage heat up unless you are operating at low current at those stages and also use heat-sinks where needed.

For extra precision, you can make it a compound opamp by adding a normal +/-15v opamp in front driving your home made one with a larger 20vpp signal.

[David Hess]

Use HV npn/pnp transistors to make this one.  The basic design illustrated makes up many simplistic audio amplifiers with +80v designs, so, I do not know how hot driving such a design with a ~ +/-260v rail will make the differential input and class A stage heat up unless you are operating at low current at those stages and also use heat-sinks where needed.

Even in lower voltage designs, the input stage and VAS may have cascodes to reduce the voltage and power dissipation requirements.  High voltage transistors usually compromise other characteristics and combining a low voltage transistor with a high voltage cascode gives better performance.

[magic]

You can try modeling and making your own bipolar op-amp, a simple one's design and function is illustrated here:

https://www.eevblog.com/forum/chat/the-history-of-the-invention-of-the-op-amp/msg5538773/#msg5538773

As shown, it's too simple for its own good, lacking essential protections

It also needs more HV transistors than strictly necessary, including a 500V complementary pair. The "boosted opamp" circuit posted by David Hess uses only a pair of 250V transistors (besides the output FETs). Note that doubled collector voltage also means doubled power dissipation and this becomes particularly important if it's a difference between running with or without a heatsink.

BTW, the IXTH10P60 seems to have enough SOA not to need stacking for 500V operation. The IXTH24N50 doesn't, but I would consider upgrading to a higher voltage part instead of stacking. It's less hassle and may end up being cheaper, too.

[David Hess]

I would be cautious about voltage ratings.  P-channel or PNP devices have lower maximum voltage ratings, so will place a lower limit on the number of devices required in series.  I would further derate the maximum voltages to 66% or even 50% for each device.

[magic]

These devices have full FBSOA specifications down to DC, one may hope this means something. While the N-ch part chosen by the OP is only speced to stand 500V for up to 10ms and demands 400V derating at DC, the P-ch does not.

Since IXYS offers 1000V rated parts, 50% derating is a possibility too.

[GN89]

Thank you for the Answers and suggestions so far. I made a completely different design without the expensive PA97 and built a fully discrete operational amplifier. Q1-Q9 form a difference amplifier. Feedback from the output comes from R16,R17. Q5 is a current source which supplies the difference amplifier current. In this case it is a high voltage pnp but it could be replaced with a low voltage one (Am I right?).

Q2,Q3,Q8 and Q9 are cascode but stacked to keep the vce voltage as low as possible. These are low capacitance PNP types. Q4 and Q6 are the load for the difference amplifier. Maybe one of you could help me with protection. When there is no vcc voltage Q1 and Q7 vbe voltage could be too high. is it sufficient to use zener diodes for protection?

Q10, Q11 form a current source for the VAS. Again these are stacked to keep them in safe operation. Maybe I will use a two transistor Mosfet current source for that to prevent secondary beakdown at all cost.

Q12 is for biasing the output stage.

Q13,Q14 are stacked and used as VAS transistors. Q15, Q16, Q17 and Q18 are the actual output stage mosfets and stacked. The simulation works and is attached but I have some questions for you. I attached transient simulation with 10kHz 5V input signal and AC analysis.

The VAS current source needs to be quite high at 8mA to have a sine wave at the output which is OK for me.

I need some quiescent current at the output to minimize prevent crossover distortion. In this case the quiescent current depends on the voltage across vg1 and vg2. How about thermal drift of the Q12 and the impact on qiescent current. I want the quescent current as low as possible. DO you have any ideas how to set this current as presice as possible?

How would I extend the output stage to allow 4 quadrant operation.

Is that a good amplifier design in your opinion and how to protect that circuit as strong as possible to prevent is from blowing up when I build a first prototype.

Offset voltage is quite bad but I yould use an oprational amplifier in negative amplifier operation to prevent that. Is that a good idea?

[David Hess]

How would I extend the output stage to allow 4 quadrant operation.

4-quadrant operation means that it can sink or source current over its entire output range, which your design can already do.

Is that a good amplifier design in your opinion and how to protect that circuit as strong as possible to prevent is from blowing up when I build a first prototype.

Vbe current limiting can use the emitter resistors at the output for fast short circuit protection.

[GN89]

I did some work on the amplifier and used different transistors for stacking to stay in the SOA of the mosfets. There is a current limitation which is done by Q19,Q20, R18,R35 and R41. R41 is important to make current limit possible in the negative half wave.

Slew rate is limited due to the high impedance drive of the mosfets by the upper current source Q11, Q12, Q13, Q14. The quiescent current setting of the output stage depends on R29 and is very temperature dependent. Do you have any suggestions how to improve the output stage to have better control over quiescent current over temperature and increase the slew rate?

[MrAl]

For some Plasma measurement I'm interesed in the development of an higher voltage linear amplifier. The basic requirement are the following:

• 500Vpp output voltage
• 100mA output current
• 1kHz maximum output frequency (maybe lower)
• Control voltage -10 to 10V

The design problem I face is how to stack mosfets and control the gates because there are few to no mosfets which have such a SOA so I need to stack them to evenly distribute the voltage.

There are some designs available on the internet but there are no real measurements and sometimes there is something obviously wrong with them. Is there any Literature for DC Amplifier design for such high voltages?

Hello,

Do you really have to use MOSFETs for this or are Bipolars ok too?

[David Hess]

Slew rate is limited due to the high impedance drive of the mosfets by the upper current source Q11, Q12, Q13, Q14. The quiescent current setting of the output stage depends on R29 and is very temperature dependent. Do you have any suggestions how to improve the output stage to have better control over quiescent current over temperature and increase the slew rate?

Thermal feedback from the output transistors need to be applied to the Vbe multiplier, either with a PN junction or a thermister.

I calculated that the VAS current is about 12 milliamps which is all that will be available to drive the output positive.  That driven into the input capacitance of the output stage will be a problem.  Amplifiers with big output transistors may buffer the drive into Q22 and Q23 using emitter/source followers or class-AB buffers.

Your topology closely follows a standard class-AB amplifier with input stage, VAS, and output stage.  Compensation is controlled by Miller capacitor C7 and the transconductance reduction from R10 and R12, but I wonder if drive to the output stage is so weak that the output stage cutoff frequency is so low that it is limiting performance.

[magic]

Did you check if slewing doesn't modulate Q12 current due to negative feedback to its gate through C10-C12? Such modulation would act to reduce slew rate unnecessarily.

Do you really have to use MOSFETs for this or are Bipolars ok too?

Do you know power BJTs good for 100mA at a few hundred volts?
It's my impression than BJTs generally have poor SOA at high voltage, and there aren't very many HV BJTs to begin with, particularly PNPs.

[MrAl]

Did you check if slewing doesn't modulate Q12 current due to negative feedback to its gate through C10-C12? Such modulation would act to reduce slew rate unnecessarily.

Do you really have to use MOSFETs for this or are Bipolars ok too?

Do you know power BJTs good for 100mA at a few hundred volts?
It's my impression than BJTs generally have poor SOA at high voltage, and there aren't very many HV BJTs to begin with, particularly PNPs.

Hi,

Why don't you do a search.
But really I just wondered if it mattered to you.

PBHV3160ZX
STN9360

[langwadt]

Did you check if slewing doesn't modulate Q12 current due to negative feedback to its gate through C10-C12? Such modulation would act to reduce slew rate unnecessarily.

Do you really have to use MOSFETs for this or are Bipolars ok too?

Do you know power BJTs good for 100mA at a few hundred volts?
It's my impression than BJTs generally have poor SOA at high voltage, and there aren't very many HV BJTs to begin with, particularly PNPs.

Hi,

Why don't you do a search.
But really I just wondered if it mattered to you.

PBHV3160ZX
STN9360

PBHV3160ZX: datasheet doesn't even have an SOA graph

STN9360: SOA graph shows it's good for about 8mA DC at 200V

...
 

[magic]

Exactly, these are switching transistors. And one shouldn't even need to read the datasheet to know that SOT223 can't handle the power dissipation of an HV output stage...