I made a first attempt to simulate the suggested circuit and extend it to a higher voltage by stacking mosfets. I had no luck simulating it with ngspice in a DC analysis. The result seems odd and the convergence is bad. Can you guys look into the schematic and tell me if the topology is correct so i can build a simple prototype?
There is one more topology which reduces HV electronics to absolute minimum.
I have used this topology before with good success. I haven't come across any source material on this (aside from being a favourite of SMU designers) - I would like to read into the background more. Does your image come from a book or article?
There is one more topology which reduces HV electronics to absolute minimum.
I have used this topology before with good success. I haven't come across any source material on this (aside from being a favourite of SMU designers) - I would like to read into the background more. Does your image come from a book or article?
The image is from Edward Cherry's Electronics World article "Ironing out distortion, part 2", where it is only used to illustrate similarities between emitter follower and common emitter output stages. There is no discussion of complete amplifiers of this kind and the topology is unattractive for audio due to the multiple PSUs requirement.
I imagine the simplest complete amplifier would add Miller compensation around this output stage and an operational transconductance amplifier in front to drive it.
For the record, this is what I meant by a simple, one chip solution for driving this grounded emitter power stage. Simulation seems to agree that it should work.
How high do you want to go? What Vpp do you want?
the open loop frequency response changes with operating point, so frequency compensation will be very difficult.
Use HV npn/pnp transistors to make this one. The basic design illustrated makes up many simplistic audio amplifiers with +80v designs, so, I do not know how hot driving such a design with a ~ +/-260v rail will make the differential input and class A stage heat up unless you are operating at low current at those stages and also use heat-sinks where needed.
You can try modeling and making your own bipolar op-amp, a simple one's design and function is illustrated here:
https://www.eevblog.com/forum/chat/the-history-of-the-invention-of-the-op-amp/msg5538773/#msg5538773
How would I extend the output stage to allow 4 quadrant operation.
Is that a good amplifier design in your opinion and how to protect that circuit as strong as possible to prevent is from blowing up when I build a first prototype.
For some Plasma measurement I'm interesed in the development of an higher voltage linear amplifier. The basic requirement are the following:
- 500Vpp output voltage
- 100mA output current
- 1kHz maximum output frequency (maybe lower)
- Control voltage -10 to 10V
The design problem I face is how to stack mosfets and control the gates because there are few to no mosfets which have such a SOA so I need to stack them to evenly distribute the voltage.
There are some designs available on the internet but there are no real measurements and sometimes there is something obviously wrong with them. Is there any Literature for DC Amplifier design for such high voltages?
Slew rate is limited due to the high impedance drive of the mosfets by the upper current source Q11, Q12, Q13, Q14. The quiescent current setting of the output stage depends on R29 and is very temperature dependent. Do you have any suggestions how to improve the output stage to have better control over quiescent current over temperature and increase the slew rate?
Do you really have to use MOSFETs for this or are Bipolars ok too?
Did you check if slewing doesn't modulate Q12 current due to negative feedback to its gate through C10-C12? Such modulation would act to reduce slew rate unnecessarily.Do you really have to use MOSFETs for this or are Bipolars ok too?Do you know power BJTs good for 100mA at a few hundred volts?
It's my impression than BJTs generally have poor SOA at high voltage, and there aren't very many HV BJTs to begin with, particularly PNPs.
Did you check if slewing doesn't modulate Q12 current due to negative feedback to its gate through C10-C12? Such modulation would act to reduce slew rate unnecessarily.Do you really have to use MOSFETs for this or are Bipolars ok too?Do you know power BJTs good for 100mA at a few hundred volts?
It's my impression than BJTs generally have poor SOA at high voltage, and there aren't very many HV BJTs to begin with, particularly PNPs.
Hi,
Why don't you do a search.
But really I just wondered if it mattered to you.
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