How does this 74LS93 circuit work?

[tjewell]

Hi all, I just cannot get my head around this little bit of circuit. It's taken from the schematics of the 80 column board of an odd French computer (the Goupil 2). So we've got a 14.7456 MHz clock hooked up to a 74LS93 which creates a sync pulse for the 6845 video chip. The output (pin 8 -> clk) seems to be running at 1.638 Mhz - the input frequency divided by 9. Which seems wrong to me, I would expect it to be divided by 10. So I'm trying to work out if this is intentional or not. But I cannot for the life of me understand how the 74LS93 is set up, with the QA and QD outputs connected to the resets and how this creates the output. Can anyone help me? Many thanks in advance!

[m k]

Those are set of dual part chips, and pretty old.

A and QA are a separated part, so B and the rest alone are an octal counter.
Connecting QA to B adds a bit and it's a hex counter.
When R01 and R02 are high the counter is zeroed, so 1001.

[Benta]

Nasty circuit with runt pulses, but that's how it was done back then.
Yes, it counts from 0 to 8 and resets at 9, so divide-by-9 is the result.
Outputs are (QC bold):
0000
0001
0010
0011
1100
0101
0110
0111
1000
1001 + QA -> RO1 and RO2 high -> reset (plus nice output glitch) -> 0000

[tjewell]

Doh! QA + QD =~ 1 0 0 1 = 9

I really should have spotted that relation. So it's working as intended, if a little bit hacky. Many thanks everyone!