DDR1 & DDR2 used a single clock, making a transfer on every rising/falling edge.
Later DDR tecnologies started to use two clock signals running at the same frequency but 90° apart, thus creating 4 clock edges, and 4 transfers pero clock (Sort of interleaving).
Really? What's your source? Can you show me an example signal from any vendor's data sheet?
Off the shelf DDR3/4/5 memories modules advertise their transfer speed in Million Transfers Per Second calling it MHz. If you read the data sheets, the DDR CK & /CK pins run at 1/2 that frequency and there is a single data transfer only once every rise and fall of that clock. IE: an advertise DDR3 1800MHz ram only has the DDR CK / #CK pins running at 900MHz.
Also note that the DDR3 minimum CK / #CK speed is 301MHz, IE: 602 MT/s, or 602MHz. (Well, for slow FPGAs, Intel sorta cheats and uses 300MHz, 600MT/s)
DavidAlfa so called 90° is the optimum timing relationship of the data bus with regard to DDR CK / #CK pins when writing data to the DDR. It is not demanded to be perfectly 90° nor are there 4 transfers per DDR CK / #CK master DDR system clock pins.