What is the meaning of DDR frequency (say DDR3-1800Mhz) how about CK/CK# pins?

[ddr_controller]

Hi fellows! Here is my situation 

I am reading the DDR3 specification from Micron https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/2gb_ddr3_sdram.pdf but cannot get around one thing:

Typically when building a PC and buying RAM, you can choose between, say, DDR3-3200MHz, DDR3-1800Mhz, etc.

Now that I am reading the docs. I cannot get around what the 3200MHz or 1800Mhz refers to... Is it the speed of CK and CK# pins?

I think it is not referring to CK and CK# as 3.2 GHz on PCB traces doesn't make much sense to me...

So what is that 3200MHz?

How fast do CK and CK# pins go?

The internal CLK in the DRAM has CK and CK# as a reference, or does the DRAM chip generate its CLK?

[ataradov]

This article https://en.wikipedia.org/wiki/DDR3_SDRAM has a summary table of DDR3 modules and corresponding clock frequencies. This whole industry is full of marketing BS. They are constantly conflating performance per chip and per bus, mixing MHz and Mtransfers/second.

In the name DDR3-xxxMHz, xxx is actually MT/s. And with the name PC3-yyy, yyy is theoretica bandwidth (MB/s). Those big numbers apply to the whole module, not individual memory ICs. Those are much slower.

[DavidAlfa]

DDR1 & DDR2 used a single clock, making a transfer on every rising/falling edge.
Later DDR tecnologies started to use two clock signals running at the same frequency but 90° apart, thus creating 4 clock edges, and 4 transfers pero clock (Sort of interleaving).

[BrianHG]

DDR1 & DDR2 used a single clock, making a transfer on every rising/falling edge.
Later DDR tecnologies started to use two clock signals running at the same frequency but 90° apart, thus creating 4 clock edges, and 4 transfers pero clock (Sort of interleaving).

Really?  What's your source?  Can you show me an example signal from any vendor's data sheet?

Off the shelf DDR3/4/5 memories modules advertise their transfer speed in Million Transfers Per Second calling it MHz.  If you read the data sheets, the DDR CK & /CK pins run at 1/2 that frequency and there is a single data transfer only once every rise and fall of that clock.  IE: an advertise DDR3 1800MHz ram only has the DDR CK / #CK pins running at 900MHz.

Also note that the DDR3 minimum CK / #CK speed is 301MHz, IE: 602 MT/s, or 602MHz.  (Well, for slow FPGAs, Intel sorta cheats and uses 300MHz, 600MT/s)

DavidAlfa so called 90° is the optimum timing relationship of the data bus with regard to DDR CK / #CK pins when writing data to the DDR.  It is not demanded to be perfectly 90° nor are there 4 transfers per DDR CK / #CK master DDR system clock pins.

[DavidAlfa]

When I said later DDR tecnologies, I didn't mean "anything after ddr2", but simply talking about other newer DDR versions in a generic way.

For example gddr5-5000, clock doesn't work at 5Ghz, uses two 2.5GHz clock signals interleaved, so the effective clock rate is 5GHz, and 10GT/s.

https://en.m.wikipedia.org/wiki/GDDR5_SDRAM

[BrianHG]

When I said later DDR tecnologies, I didn't mean "anything after ddr2", but simply talking about other newer DDR versions in a generic way.

For example gddr5-5000, clock doesn't work at 5Ghz, uses two 2.5GHz clock signals interleaved, so the effective clock rate is 5GHz, and 10GT/s.

https://en.m.wikipedia.org/wiki/GDDR5_SDRAM

Show me a clip from an actual manufacturer's data sheet.  Do not trust Wikipedia.

And do not come around and claim you meant QDR ram, or count separate read and write ports as 2x data.

[magic]

DDR is supposed to stand for "double data rate". I.e., two transfers per clock.

Even that nonsensopedia article states that for a 5Gb/s GDDR5 chip, the data clock runs at 2.5GHz but there is also a command clock at half that.

No quad clocking anywhere in sight

For standard RAM, every CPU spec sheet, BIOS, etc. states that frequency is half the advertised "speed" of the module. Latencies are counted in clock cycles equaling twice the advertised transfer time.