50MHz Signal- does it need impedance controlled routing ?

[YaSaRa_N]

Hi, I am working on my university project of designing a device for testing digital ICs (simple ones like microcontrollers, SPI flash memory, etc). I am testing the digital functionality of the IC by sourcing digital signals (pre-determined) to the IC's input pins and capturing the outputs and then by comparing those captured outputs with the expected outputs (like a truth table).

I am planning to use an FPGA dev board (Altera DE0-nano) to source the signals and capture the outputs. It has only 3.3V logic standard, but I intend to test ICs using several logic level standards (1.2V-5V).Therefore I am planning to use a logic level translator (74LVCH2T45D) in unidirectional mode. The schematic for sourcing 2 digital signals is shown below.



I  am making a PCB with this logic level converter which can be plugged in to the FPGA. The relays in the schematic are just for connecting/disconnecting the digital I/O ports on my device. Currently I am designing my interfacing PCB in a 2 layer board without any impedance controlled routing. My target in to achieve a 50Mhz data rate somehow. I need your opinions on some of my doubts mentioned below.

1. Is it possible to achieve 50Mhz with reasonable signal integrity (with square shaped pulses) without impedance controlling in this PCB?
2. Should I be using any termination resistors in the signal paths? If so what is the best method of termination?

Note: Since I am making this to test any general IC, the load resistance of the signal can vary

[TimFox]

If you are putting fast signals through series resistors R2 and R4 = 1k, I don't think impedance-controlled routing will make any difference.  For lengths less than, say, one meter, the traces will look like capacitors to ground.
One technique that may be useful is to "series terminate" the signal with 50 ohm resistors at R2 and R4 (assuming a 50 ohm characteristic impedance) with high-impedance termination at the far end.  This will give you full voltage at the termination, but if the transmission line is a mismatch to 50 ohms (which should include the output resistance of U4), you will get a small reflection at the source back to the load.

[YaSaRa_N]

I thought of putting those 1k resistors for protection of the device. You said that without impedance controlling my trace would look like a capacitor to ground. So, should I be worried about that in dealing with a 50MHz signal. Should I be worried about impedance controlling for a 50Mhz data line?

[TimFox]

A short length of transmission line (electrical length < 1/8 the period of your signal, or so) will look like a capacitor regardless of its characteristic impedance, although the capacitor value depends on the length and other parameters of the line.  For comparison, RG-174/U 50 ohm coax is about 1 pF/cm in short lengths, with an electrical length of about 50 psec/cm.

[tggzzz]

I am testing the digital functionality of the IC by sourcing digital signals
...
My target in to achieve a 50Mhz data rate somehow.
...
1. Is it possible to achieve 50Mhz with reasonable signal integrity (with square shaped pulses) without impedance controlling in this PCB?

Be aware that your figure of 50MHz is highly misleading w.r.t. signal integrity.

Signal integrity is dependent on the highest frequency in a signal, not its repetition frequency[1]. The only relevant figure is the rise/fall time, since that determines the highest frequency in the signal. Then compare the length of the connection with that frequency or transition time.

[1] experiments illustrating the theory at https://entertaininghacks.wordpress.com/2018/05/08/digital-signal-integrity-and-bandwidth-signals-risetime-is-important-period-is-irrelevant/

[Vovk_Z]

1k series resistance may be too much for high-frequency signal. It depends on a capacitance after this resistor.

[Siwastaja]

What tggzzz said; but note those 1k resistors will limit the rise/fall times so slow that you can't achieve the communication at 50Mbps because the signal settles slower than the time required to transmit one bit. (I'm confident enough to guesstimate this. Say, assuming even just 20pF trace & pin capacitance, R*C = 1000 ohm * 20 pF = 20ns, actually equal to your period at 50MHz, so wasting the complete period just to settle to 63% of the target voltage!)

OTOH, wasting some 5-10% of the period available for smoother transitions does help with EMI, so having some resistance is desirable.

I would do a very roughly impedance controlled line, i.e., use a 4-layer (or more) design because you likely have it already (or greatly benefit from it in such FPGA project), look at the stackup your board vendor uses, then use some sort of trace width calculator so I end up at some known impedance such as 50 ohms or 70 ohms, roughly.

Then, use series termination (resistor in series with the driving pin) approximately the trace impedance minus the output impedance of the CMOS output driver. The latter is actually a range depending on unit variation, temperature, etc., and not properly specified, if at all; assume the lowest possible here so that we rather oversize the resistor than undersize it, to prevent ringing. For example, assuming Zout = 10 ohms, Ztrace = 60 ohms, use a 50 ohm series termination resistor.

The larger it is, the slower the transitions, the smaller the current spikes to drive the line, the less ringing you see. I would use some 47R to 68R.

But at 50Mbps transfer rate, you don't have a huge margin to slow down the edges, so 1k will definitely fail.

Your 1k together with parasitic capacitances and junction diodes provide indeed better ESD protection than adding just some 50R. But seeing this is on-board communication, just internal signals, such protection isn't usually used because it would be quite hard to zap those internal signals (normal board handling precautions apply!) If you went that way, you would want to consistently protect every signal and that would make everything impossible. (IC manufacturers add enough protection into their ICs so they handle "typical" board handling conditions.)