Controlling Voltage of Digital Input Signal for R2R DAC

[ChalkyChalkson]

TLDR; I have a digital input signal of unknown voltage. I do have a known reference voltage available. I would like to combine the two in a way to get a digital signal with the same content as my input, but with the high/low potentials determined by my reference voltage. Basically I want a relay but without the clicky stuff...


Hi!

I decided I wanted to learn more about (analog) electronics and decided an R2R DAC with an INA125 for the ladder input voltage and amplification was as good a place to start as any.  The actual R2R part, amplification and low pass filter were drawn up pretty quickly, but I didn't manage to figure out how to deal with the inputs. If I want the output range of the DAC to be independent of the digital high voltage I need to somehow also control the voltages that go into the ladder, right? I thought """ANDing""" together the digital signal and my Vref would be trivial (and it kind of is with relays), but after two days of banging my head against a wall I'm ready to ask for help.

Requirements
Inputs: GND, 1bit digital input, Vref
Output: if digital input is high Vref, else 0V
Other:

• low current drawn from Vref source (if necessary I could always an opamp and circumvent this
• fast-ish would like to do at least 20KHz switching, ideally 100KHz
• no "cross-bit" contamination (ie preserve linearity of the R2R stage)
• voltage of high input should not impact output

What I tried
Being a physicist not an electrical engineer, a FET looked a lot like a relay to me (from far away that is), so that was my first idea. (The 4 5V AC sources at the top are configured to put out square waves at 1,2,4,8 Hz to simulate every possible input in a ramp shape. After testing these will probably become a shift register.)
It looked sensible, but I decided to simulate it with SPICE in Fusion. It told me that adding FETs like this (also tried P-type) would completely destroy my linearity.
As a sanity check I ran the same simulation without the FETs and that had a linear output. The same issue also arose with transistors.



One thing that I thought was very weird: the non-linear contribution seems to depend more on how many bits are active than the output voltage (though that seems to contribute, too). A working hypothesis was that maybe when the output voltage gets close to the input voltage the potential drop between gate and source becomes too low, but dropping Vref or increasing the digital input voltage doesn't help. And that wouldn't have fit the pattern anyway.
I also thought it might be an issue with the source to ground resistance being so different between the FETs, but that also didn't fit the pattern, and trying to alleviate the issue with diodes and resistors also didn't work.
Then I tried connecting the low potential of the digital inputs to the output of the R2R ladder. That makes it better, but it doesn't solve the issue completely and it's also not really doable with the physical circuit as I don't want my arduinos ground to become 5V relative to earth.

Ready to give up on individual FETs for a moment, I considered using an LS compatible bus transceiver, inverter or some other simple logic chip and just driving that with Vref as VCC. In simulation that obviously works, but there is also magical DTOAB and ATODB involved. I am concerned about that solution since
A: What is a logic chip other than fancy FETs and transistors, so who tells me the issue isn't going to occur there? And
B: I don't have the equipment to measure it yet, but I doubt stability and accuracy of output voltage are a huge design concern for logic ICs.

Since what I want is basically an amplifier deep in the saturation regime I also read a bit about FET amps and decided to try a more normal FET amp layout

The issue persisted.

What I tried to find
After some time I decided to look around for other peoples' solutions. But I don't know what the thing I'm trying to do is called, so all I could think of is looking at circuit diagrams of other DACs. Issue is R2R seems not the most popular one for actual builds and most of the circuits people draw online just skip this step. Or they do it like TI and draw switches... Also ended up watching two community college lectures on R2R DACs that were on YT, but they also didn't deal with that.

Where I'm at now
Given all that, I think I need something that behaves even more like a relay. If I don't find a good solution, I'll probably end up using relays themselves. But this feels like the sort of problem with a well known solution... If you happen to know one or understand the weird non-linearity of the spice output, I'm very willing to learn

Level of knowledge
I know very little about AC stuff, circuits that can't be represented well using complex voltages and impedances are black magic to me, so if your answer involves anything regarding the high frequency content of a square wave, please be gentle. I don't have much experience with FETs, I mostly treated them as slightly weird transistors that need a charged capacitor instead of a current. But I'm pretty comfortable with some maths in my learning, especially when it's (complex valued) Kirchhoff's or Ohm's laws in disguise
I strongly suspect however that the answer is going to be something really stupid....

Thanks for reading this overly long blurb of my  ! Looking forward to your answers

[oPossum]

74HC4053, DG2524, and such.

[oPossum]

I considered using an LS compatible bus transceiver, inverter or some other simple logic chip and just driving that with Vref as VCC.

74AHC573

74AHC family allow inputs to exceed supply voltage (up to 5V)

[ChalkyChalkson]

That looks like it should do it! I kind of expected an answer to look like that
Just to be sure, I should connect Vref and GND to Y0 and Y1, the R2R to Z and my digital input to S?

 Still interested in learning why this much more complicated FET structure is needed, but I'm very happy I can finally order parts!

[Ian.M]

The principle of a R-2R DAC requires each lower stage of the ladder to present a constant source impedance of 2R to the next stage.  Consider the LSB stage - it has 200K to ground as there are no lower stages, effectively in parallel (for its Thevenin resistance) to the 200K to the LSB digital output, and 100K in series to bring the total output impedance back up to 200K.  For it to maintain constant output impedance and work by making a binary weighted contribution to the total output, the digital output must switch voltage levels between RefGnd and Vref, not open/close a circuit to a single voltage level.

Here's a LTspice sim of an eight bit R-2R DAC, using LTspice bussed component notation to repeat the MOSFETS and ladder stage resistors eight times, and hook up the stages in the correct order.

As you can see it produces a linear ramp between 0V and Vref as the voltage sources' pulse waveform for each gate count in inverted binary.  If you delete the visible N-MOSFET (lower one) it removes all eight instances of it, making the output impedance dependent on the binary input, and the result will then be the same erroneous one as your simulation.

Also note that you must have Vref>>V_{GS_threshold(max)} so the difference between it and logic '0' is enough gate drive to fully turn on the (upper) P-MOSFETs.

N.B. Strip the extra .txt extension from the .plt plot settings file. 

[Kleinstein]

For a R2R DAC the signal to the resistors needs to have the same output resistance for the high and low state. So it needs usually 2 FETs to switches, one for the GND and one for the V_REF side.

If the reference voltage is fixed at some 5 V or similar voltage suitetable for logic chips, one can use logic chips with CMOS output, like the mentioned 74AHC573, but also other types are convenient like 74HC541  74HC244  HC245. The suitable series  ( AHC, HC, HCT, LV, ...) depends on the voltages.

If the Ref. voltage is variable, it would take more like CMOS switch chips like the  74HC4053 or similar, also depending on the voltage range.

[Berni]

You need a transistor push pull output stage to drive the elements of a R2R DAC. This just happens to be what the output of a digital pin is. So buying a standard 74xx hex buffer chip is simply getting all the transistors you need packed conveniently into one component.

The thing to watch out for is symmetry. The P and N channel transistors on top and bottom are made trough different manufacturing steps so they are not identical in performance. So in some logic families you will find that the maximum high level output current is much lower than the maximum low level output current. This is because the Rdson of one FET type is much worse. This resistance gets added into the resistance of the R2R resistors. So a good start is to use logic families that spec the same number of mA for both high and low output levels. This still won't mean the P and N FETs have an identical Rdson, but at least they will be fairly close (rather than one being 2x to 4x the other).

[DavidAlfa]

The 74HCT244 buffer is a good option.
Whatever you Vref is, just set high input resistor values (100K+) and any negative / excess voltage will be clamped by the input diodes without damaging anything.
Using those 200K for 2R, the fets Rdson assymetry would be negligible, e. 20 and 500 Ohms would make a 0.25% difference.

[ChalkyChalkson]

The principle of a R-2R DAC requires each lower stage of the ladder to present a constant source impedance of 2R to the next stage.

I think I understand now. When the FETs were not switching I ended up with the thevenin equivalent resistances being all over the place so it behaved weirdly.

So buying a standard 74xx hex buffer chip is simply getting all the transistors you need packed conveniently into one component.

I have quite a few 74LS245 left over from another project, I think they should work.. According to the TI datasheet it either pulls the output to GND directly or via a 50Ohm to VCC. Also uses all the same type of transistor. So with a 50Ohm to GND and Vref to VCC I should be good, right? The bidirectionality and tristate-ness are a bit of a waste, but rather use some of the chips I have than buy new ones

[Ian.M]

Nope.  74LS245 is BJT TTL and has outputs with a NPN Darlington high side transistor, with a pull-down on the driver emitter so its logic '1' will be an ill-defined load dependent and temperature sensitive level typically around volt or so below Vcc.  See T.I. datasheet 'Figure 4. Schematics of Inputs and Outputs'.

Use just about any CMOS logic for outputs that actually swing rail-to-rail.

[Berni]

You also don't want the R2R resistor values to be too high.

This can cause problems with high speed operation because parasitic capacitance start to mess up the timing of it. At the same time this makes the output fairly high impedance, so amplifying that to a nice low impedance signal is more noisy at wide bandwidths.

In general running R2R DACs at high sample rates to generate a continuous signal requires careful design. Very slight variances in the timing between bits (and other parasitics) results in some bits updating sooner than others, causing the output of the DAC to actually briefly jump to the wrong code before settling into the right one. This injects some glitch energy into the output every time the DAC is updated (this tends to be the worst when updating the MSB bits). Once the signal is passed trough reconstruction filtering these brief glitch pulses get incorporated into the signal. This causes extra noise and distortion when reproducing a sine wave for example. For low bit depths this is not so much of a problem as there are so few bits and the resolution is so low the glitch is smaller than the LSB bit, going past 8bit it becomes a big problem.

[ChalkyChalkson]

You also don't want the R2R resistor values to be too high.

Ok so I'll have to add another opamp or other voltage regulated source to get a higher current source of my Vref, then use smaller resistors for the ladder. Like 100-200Ohm maybe 10-20? Don't really want to deal with much more than a couple mA in there.

Very slight variances in the timing between bits (and other parasitics) results in some bits updating sooner than others

What is a good way to deal with that? Match the capacitance and inductance of the bits with trimmable caps? I was going to put a second order active RC lowpass in there. Maybe also making the cutoff digitally selectable. This is primarily intended as a DC source, but I would like for it to play audio, so I'm designing with 10s of kHz in mind. You think parasitics will already be a big deal in that range? I gotta admit I was kinda hoping to assemble everything with DIP components, if parasitics matter that's probably a bad idea and I'll have to deal with SMD...

For low bit depths this is not so much of a problem as there are so few bits and the resolution is so low the glitch is smaller than the LSB bit, going past 8bit it becomes a big problem.

Well I drew it with low bit depth here, but I was hoping to go like 12-16bit.. Is it sensible to try to deal with that by feeding the output into a sample and hold circuit and only updating that a certain time after the inputs where updated? Seems kind of brute force-y to me if I'm honest. But I don't know how else I would deal with that

[oPossum]

Audio DACs are typically delta-sigma rather than pure R2R. Much less expensive to do it that way. 16+ bit R2R DAC chips do exist but they are quite expensive.

6 bits is possible with 1% resistors and maybe 8 bits with 0.1%. Beyond that it becomes rather impractical to do a discreet design. Precision is required to keep the DAC monotonic.

An example of a not quite monotonic 8 bit R2R DAC...

[Ian.M]

16 bit audio R-2R DAC with discretes and LSI logic?    You are crazy!   

The accuracy of a R-2R DAC is determined by how well the resistors match.  Consider the MSB transition, which crosses from all lower bits set to just the MSB set (or visa versa).  The step *SHOULD* ideally be the same as the LSB step size, so just to get the step in the correct direction (i.e. a monotonic DAC), assuming a maximally pessimistic tolerance stack-up with the top bit 2R at one limit and all lower resistors at the opposite limit the tolerance must be better than +/- 1/(Nbits+1).  To get no more than 1/2 LSB nonlinearity error it must be better than 1/(Nbits+2).   Assuming you get  $EXPEN$IVE$ 0.01% tolerance resistors, that gets you 13 bits of reasonable linearity, and just lets you scrape in with a 14 bit monotonic DAC provided the contribution of your switch or logic output on resistance is small compared to your 2R resistor tolerance.   As the typical output resistance of CMOS logic is several tens of ohms, (depending on family and Vcc), that limits the minimum 2R value for a monotonic 14 bit R-2R DAC driven direct by logic to a bit under 1Meg (again depending on family and Vcc).

Berni has already pointed out how that limits the max bandwidth.  e.g. if the output impedance of the DAC is 1Meg, even 10pF of stray capacitance gives you a low pass with a 15.9KHz -3dB corner frequency. 

oPossom was being excessively polite when he said "... rather impractical ..." - Unless you've got extreme audiophool levels of cash to throw at metrology grade resistors and extremely low on resistance analog switches, and are willing to hand-select the highest few bits resistors for best matching anything past 12 bits is just a waste of time and effort, and even 12 bit will cost you *serious* money. 

For those of us with thinner wallets and more common sense, the break-even point is certainly no more than 8 bits as precision passives cost money, and by the time you've added up the costs of all the resistors, the extra digital outputs, the essential buffer amp, board area and a screening can, you might as well have dropped in something like a SPI DAC which will almost certainly give you better performance for similar cost.

[Kleinstein]

With an R2R DAC the LSB part can be lower accuracy. The lower 6-8 bits are relatively reasy, but the next bit need about double the effort for each bit. The number of resistors is not so bad, but requirements on accuracy (maybe trim) and stability (you likely don't want to repeat the trim every hour).

Typical logic like 74HC are in the 50 Ohms range and have a mismatch in maybe the 5-10 Ohms range. CMOS switch chips may have slightly better matching, but are still not perfect. One can at least compensate for the typical swtich resistance, but hardly for the difference. There are some ways around this, but it is tricky and tends to be slow.

[ChalkyChalkson]

Ok, seems like I seriously underestimated how badly this circuit depends on the performance of its components. 8-10 bit it is then. And probably 10-15kHz low pass.
Was kinda hoping to help the precision of the ladder by getting one of these resistor banks which better relative than absolute precision. But your overall point clearly stands.
Audio was an afterthought anyway so I'm happy trading a lower frequency cutoff for at least 0.1% resolution for the output voltage.

This was mostly intended as a little project to learn a bit more about analog stuff. 1 byte of precision just sounded so low to my digital brain... 
 

74HC are in the 50 Ohms range and have a mismatch in maybe the 5-10 Ohms range.

Yeah I was worried about that... Was considering putting an opamp behind the output but that's probably getting into stupid territory and just shifts the burden of accuracy to another part.
Probably going for 10bits and .1% on the lower ones and 0.05% ones for the two-three msb

[Berni]

16bit Audio DAC is going to be rather difficult in R2R

The accuracy of the MSB bits matters a lot since if they are off by only fractions of a % that will cause a error larger than a few LSB bits. The timing problems also can't just be solved with low pass filtering because the glitches produces are not purely zero centered AC, they have a DC component to them that the low pass filter lets trough.

As others have said delta sigma is a much easier way of achieving these high resolutions. All the high performance 24bit audio DAC chips are actually 1 to 6 bit DACs (often with identical elements that get cycled around) and then modulated to get the rest of the bits to 24bit.

You can actually get R2R type topology DAC chips to 16 bits and some. They way those are produced is using laser trimming for the on die resistors at the factory to get them spot on, then those are also binned in grades to pick out the best performers. This makes them expensive, so it is not really done anymore.

[Ian.M]

Here's another sim - I pulled the top two bits out of the bussed component group so I could do a worst case tolerance stackup for the resistors of the top two bits *ONLY*, zoomed in on the MSB transition.   N.B it assumes bits 0 to 5 of the ladder are nominal, so if for instance the 2R resistors are off nominal in a systemic manner, and you had a couple of outliers in the opposite direction in the top two bits, it could be even worse!

See https://www.analog.com/en/technical-articles/ltspice-worst-case-circuit-analysis-with-minimal-simulations-runs.html for method.

[strawberry]

digital potentiometer

[ChalkyChalkson]

Here's another sim

Thank you so much for your help! I'm still in the process of learning spice, so your sims to show the impact of imperfections were really helpful in understanding

I've settled now for a much less ambitious design with 8bits. Some basic gaussian error propagation tells me that 0.25% resistors should get me there. The DC component of the switching error I think I won't deal with (even though it pains me). But after I have something cheap-ish that works I can still go back and try to design something better.

Looks like this forum has an infinite number of threads with people describing their builds of insanely precise devices...