Author Topic: Constant Current Load Stability  (Read 7293 times)

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Offline sorin

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Re: Constant Current Load Stability
« Reply #50 on: May 18, 2023, 08:13:48 pm »

So, maybe instead of posting more clutter you might want to read what has been written en discuss how to compensate the loop properly (yes, there is room for improvement). Instead you add in your mall functioning experience. That math involved isn't complicated at all in this simple circuit.

Please can you tell us what is a mathematical way to calculate the optimal capacitance (C2) in this situation?
It is obvious that 5nF or larger capacitance is a nonsense.
 

Offline Avelino Sampaio

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Re: Constant Current Load Stability
« Reply #51 on: May 18, 2023, 10:21:30 pm »
In the transient test of a PSU, the drain voltage variation is very small (maximum of about 200mVpp). The gate voltage orbits around 4.5v. The Mosfet in this case always works in the linear region.  For Cgd to have any influence, and I consider it little, the PSU output must be below 4.0v.

That's an interesting discussion. Anybody willing to do a spice simulation?)

In my limited experience, drawing more than a milliamp or two reduces opamp bandwidth. So, I prefer to do sziklai/darlington, that improves transient response. The question is how fast it needs to be. Too much bandwidth won't do good for a general-purpose power supply with long leads and "difficult" load.

In this project of mine I am using the OPA172 to drive the IRFP460 linear mosfet, which has a Qgs of 29nC. Note in the images that the duo behaved very well in the transient test of my PSU.

PSU at 8v with pulse current applied around 1A
The applied pulse has an edge slope of about 8µs.

1 - schematic
2- 200µs pulse on the gate
3- 200µs pulse on the source
4- PSU response to the 200µs pulse. Much of the 200mVpp is due to the resistance of the long cable I used.
 

Offline Avelino Sampaio

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Re: Constant Current Load Stability
« Reply #52 on: May 18, 2023, 10:24:20 pm »
Follow the test with a pulse of 50µs and edge slope of 8µs

1- 50µs pulse at the gate
2- 50µs pulse at the source
3- PSU response to the 50µs pulse
 
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Offline Avelino Sampaio

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Re: Constant Current Load Stability
« Reply #53 on: May 19, 2023, 11:26:41 am »
I forgot to mention two details:

1- The 8µs rising edge slope was obtained using the cny17-2 optocoupler.
2- A DC floor (10%) is always kept on the wrist, to keep the Mosfet always on. This ensures a smaller effect of the Qgs charge.
R6 is responsible for the DC floor.
 

Offline temperance

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Re: Constant Current Load Stability
« Reply #54 on: May 19, 2023, 03:42:42 pm »
Calculating the feedback capacitor:

1. The pole introduced by the limited drive capability. The gate resistor is 300Ohm + 1K. The 300Ohm is taken from an LM324 data sheet. That's the open loop output resistance of the op amp. (we can't supply more current)

What do we get: Ciss of the IRF240 increases with decreasing drain voltage. This causes the  phase shift being introduced into the feedback loop to shift left and right. (The gain and phase is measured across R2 because that's what's being fed back into the op amp.)

As shown the phase shift occurs well below where the op reaches unity gain. The total phase shift at the unity gain frequency is now >>180°. Or, an oscillator.

2. Compensating the op amp:
With a 10K feedback resistor and 1K3 gate drive resistance and drain voltages being taken as low as 1V (Ciss increases with decreasing drain voltage), the minimum feedback capacitor to compensate for the pole must be 1 / (2 * 3.14 r * f)= 1 / (2 * 3.14 * 10K * 50K)= 318pF

This results is a load with sloppy response.

3. Decreasing the gate resistor in order to improve the step response:
nice idea. But op amps aren't ideal. When driving a capacitive load, something called gain peaking occurs. More on that in this app note:
https://ww1.microchip.com/downloads/en/Appnotes/00884b.pdf

The app note doesn't show the phase shift at this gain peak. But the circuit, being an imaginary inductor driving a capacitor will change it's phase above resonance. The bandwidth and maximum phase shift are determined by the network Q factor. Low resistance, or low gate resistors imply a larger phase shift. I didn't bother to calculator the inductor value based on the app note. But one can see that this will happen way before the op amp reaches unity gain.

An extra buffer amplifier:
An extra buffer isolates the MOSFET capacitance from the op amp and places the pole introduced by the low output impedance driver well above the unity gain bandwidth of the op amp.

I'm not going to investigate if the OPA172 will work properly because at first glance, the open loop output impedance is not defined.



« Last Edit: May 19, 2023, 05:03:25 pm by temperance »
 
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Offline MrAl

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Re: Constant Current Load Stability
« Reply #55 on: May 21, 2023, 10:16:05 am »
Hi again temp,

That sounds like a very good analysis, i have to praise anyone who takes the time and effort to look at these kinds of circuits in that detail.  Very good work i am impressed, and i trust you enough to believe you got it right.

One other thing i did learn in the past i forgot to mention in current feedback circuits (i know this is a little different but it deals with current too) is that if the driven device is much faster than the, say, op amp, and has good compliance, the circuit usually works even without compensation.  That i think is because the driver can follow the (op amp) almost perfectly and that means the op amp gets its normal feedback signals.
There could be exceptions i guess, but one example is when adding a single transistor to add current feedback to a voltage regulator.  The idea of course is to implement a known current limit when that is not built into the voltage regulator, especially when we want some adjustment too.
A single bipolar with current sense resistor (any maybe a diode) can sense the current level and provide "OR'ed" feedback to the voltage regulator, thus implementing current limit.  The transistor is so fast that the regulator probably sees it as not even being there.
Just something to think about, but as i said there could be exceptions.
I think that to get this to happen with a MOSFET we would need to introduce a decent gate driver too, maybe a complementary bipolar pair.
Would be very interesting to see that if you feel like trying it.
 

Offline temperance

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Re: Constant Current Load Stability
« Reply #56 on: May 21, 2023, 03:16:38 pm »
Quote
One other thing i did learn in the past i forgot to mention in current feedback circuits (i know this is a little different but it deals with current too) is that if the driven device is much faster than the, say, op amp, and has good compliance, the circuit usually works even without compensation.

Isn't that exactly what I did by buffering the op amp such that the pole created by the buffer MOSFET combination is way above the unity gain frequency of the op amp. Indeed, in such case you don't need any compensation. You can add some compensation if you want to limit the slew rate. Or just take a much slower op amp.

In general, this is called dominant pole compensation.

Quote
I think that to get this to happen with a MOSFET we would need to introduce a decent gate driver too, maybe a complementary bipolar pair.
Would be very interesting to see that if you feel like trying it.

Now I'm confused. I presented such a circuit here:
https://www.eevblog.com/forum/beginners/constant-current-load-stability/msg4864031/#msg4864031

And demonstrated a quick and dirty working circuit here:
https://www.eevblog.com/forum/beginners/constant-current-load-stability/msg4865513/#msg4865513


Best regards
« Last Edit: May 21, 2023, 03:46:33 pm by temperance »
 

Offline MrAl

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Re: Constant Current Load Stability
« Reply #57 on: May 21, 2023, 09:16:22 pm »
Hi,

Oh ok very good  :)
 

Offline johhnyboyer

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Re: Constant Current Load Stability
« Reply #58 on: August 16, 2024, 11:07:11 am »
@ temperance


A fast responding dummy load which doesn't oscillate with jelly bean components. The disadvantage being the quiescent current in the totem pole buffer stage and the current trough R2. In total something like 5...7mA.
-D4 and D5 make sure that the input of the buffer stage can be driven to GND.
-C2 assists on "eating" the current injected trough drain gate capacitance if a transient appears on the drain.
-C1 and R5 compensate parasitic inductance introduced by the cables connected to the drain. C1 is a film capacitor, any type, nothing fancy. R2 must be a 1..3W resistor depending on the input signal.
-Q1 and Q1: any "normal" transistor will do. BC547, BC557...
-All small signal diodes: any small signal diode will do. 1N4148, 1N917, BAS318, BAV70,...
-The LT1014 is a low offset version of the LM324.


I've looked at this quite a bit and I like it. There are a couple of things that I don't understand.

a) Later on in the thread you said "the value I've chosen for R3 (by some ruff guess) seems a little high. 33R would be more appropriate"
Here I assume you mean R1 and not the current sensing resistor on the low side.

b) Also later on in the thread you said "R2 must be a 1..3W resistor depending on the input signal."
I can't see why this 4K7 resistor can't be a plain 0603. Current shouldn't be more than 5-10mA?

c) I still don't understand the purpose of the two diode sets (D1-D3 and D4-D5)

Thanks!

-- john
 

Offline temperance

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Re: Constant Current Load Stability
« Reply #59 on: August 29, 2024, 08:12:29 pm »
a) Later on in the thread you said "the value I've chosen for R3 (by some ruff guess) seems a little high. 33R would be more appropriate"
Here I assume you mean R1 and not the current sensing resistor on the low side.

Seems to be a mistake. That must be R1 as you stated. This resistor sets the quiescent current in the totem pole buffer. An other option is to make the bias voltage (D1...3 adjustable)

b) Also later on in the thread you said "R2 must be a 1..3W resistor depending on the input signal."
I can't see why this 4K7 resistor can't be a plain 0603. Current shouldn't be more than 5-10mA?

An other typo it seems. That must be R5 in the snubber network. The snubber network cancels the inductance present in the drain connection. Omitting the snubber will result in oscillations because the drain inductance forms a tuned circuit together with the MOSFET output capacitance.

c) I still don't understand the purpose of the two diode sets (D1-D3 and D4-D5)

D1...3: they generate a fixed bias voltage for the totem pole buffer. A more fancy version would be to replace R4 with a current source and replace the diodes with trim pot.
D4...5: they allow the voltage across R2 to go below the negative saturation voltage of the op amp. They might not be required for a rail to rail output amplifier.

-The input of the op amp must be able to work with voltages very close to GND.
-The op amp input off-set voltage translates into a current off-set equal to Vos / Rsense
-The MOSFET must be a type with a high threshold voltage because the totem pole driver keeps the gate at minimum 0.6 V. Something above 4 V will do fine. See data sheets for gate source versus drain current characteristics.
-Don't use modern MOSFET's but old types like an IRFP240/250 or use something like this:
https://www.littelfuse.com/products/power-semiconductors/discrete-mosfets/n-channel-linear.aspx

I hope this helps to get it to work properly.
 


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