Constant Current Load Stability

[temperance]

I see what you want to do. but this is not going to be stable with temperature. To compensate that you need some kind of current mirror approach.

[exe]

I see what you want to do. but this is not going to be stable with temperature. To compensate that you need some kind of current mirror approach.

Opamp handles that. I think a few kHz loop bandwidth should be enough. I'm making a test pcb to thoroughly test this approach.

[exe]

I just assembled a current sink with mc3302, 1 Ohm resistor and PSMN9R5-100XS fet (last plot, I messed up attachments), no compensation whatsoever.Orange trace is shunt voltage, blue is gate drive. The test is 0mA-200mA step (applied to opamp's Vin+) I guess it's safe to say it needs compensation .

Then I replaced the mosfet with D965 bjt of suspicious origin, and, guess what, looks like response is much better (first plot)

The second plot is made with BS170, a small fet from onsemi. It looks the best, imo.

I tried to do the shortest wiring possible, and added a few 1uF decoupling caps. NB the second opamp is not used, and left floating in the air. But it seems it doesn't oscillate (as seen on output), so we good there.

[TopQuark]

Hi,

There are a lot of issues that can come up here with a circuit like this.

The first is the MOSFET.   These have capacitive inputs and thus are harder to drive.  A biploar would be simpler.

The second, probably even more important, is that regulator circuits that use the source (or emitter) connected to the sense resistor and use the drain (or collector) as the current output (or input) makes it a much harder circuit to compensate and for a general load and it may actually be impossible to compensate.  That's because the different kinds of loads you can encounter could have resistance combined with capacitance and/or inductance, and that just doesnt work.  To get it to work you would probably need some minimum capacitance on the load, which means actually adding some permanent output capacitance.  That's the way it is with these circuits because the transistor provides an increase in loop again, and it could be a lot, and that means the internal compensation of the op amp is no longer effective in keeping the circuit stable.  This i could guess is the major problem.

To rectify this, change the circuit into a circuit that uses the source (or emitter) of the transistor as the OUTPUT while possibly also sensing current in the source (or emitter) but you could also try sensing in the drain (or collector).  What this does is it reduces the voltage gain of the transistor to less than 1 and makes it easier to stabilize.  This is the most likely to work as you need with a more general type of load.

What you should probably do is start with a bipolar transistor and go from there.  Once you get it working if you really think you need a MOSFET then switch to that and rework the design a little.  In that case you should really use the source terminal as the output though not the drain as mentioned above.

Opamps driving mosfets to form a dynamic load is nothing new and not that difficult if you are not aiming for very high control bandwidth. Numerous commercial MOSFET-based programmable loads offer dynamic loading function with programmable slew rate, usually in the range of few A per us. They don't oscillate even if the DUT is connected with meter-long cables.

Hello,

I have been trying to make a constant current load powered from a 9V battery as a little project and I've been having stability issues with the op amp oscillating.

You can have a look at my project as a base to improve on. 0A to 50A in 283ns (>1MHz BW), no oscillation and minimal overshooting.

https://www.eevblog.com/forum/projects/gt1mhz-bandwidth-electronic-load/

My project is more of a skill building exercise rather than trying to design a general commercial product, so it is not designed to perform well with inductive loads, and it doesn't. You can add a RC snubber between the two load terminals, or add more phase margin and lower the control BW to make it more suitable with general loads.

The way I see it, there's two ways of designing a stable closed loop controlled DC load.

The professional way would be to model the components you are going to use, build a simulation, find the poles and zeros in the plant (the thing you are controlling), design your type 1/2/3 compensator, placing the compensator poles and zeros in a way that maximises your system open loop bandwidth (crossover frequency) and stability (phase margin). This probably won't account for the crossover distortion of the LM324 however.

The intuitive way (or at least how I think about it) would be to make sure the thing you are trying to control responds faster (how fast your opamp output can drive the MOSFET, and how fast the feedback signal arrives back to the control opamp) than how fast the opamp is trying to control it (i.e. the gain bandwidth of the feedback loop).

So the gist of it is to use an opamp with high drive strength (or add a high current buffer amp like in my design), MOSFET of low gate capacitance then roll off the control gain-bandwidth by increasing C2 until it is stable. You can shape the response further by placing a cap in series with R6 etc. , but the above steps should be sufficient.

[MrAl]

Hi,

There are a lot of issues that can come up here with a circuit like this.

The first is the MOSFET.   These have capacitive inputs and thus are harder to drive.  A biploar would be simpler.

The second, probably even more important, is that regulator circuits that use the source (or emitter) connected to the sense resistor and use the drain (or collector) as the current output (or input) makes it a much harder circuit to compensate and for a general load and it may actually be impossible to compensate.  That's because the different kinds of loads you can encounter could have resistance combined with capacitance and/or inductance, and that just doesnt work.  To get it to work you would probably need some minimum capacitance on the load, which means actually adding some permanent output capacitance.  That's the way it is with these circuits because the transistor provides an increase in loop again, and it could be a lot, and that means the internal compensation of the op amp is no longer effective in keeping the circuit stable.  This i could guess is the major problem.

To rectify this, change the circuit into a circuit that uses the source (or emitter) of the transistor as the OUTPUT while possibly also sensing current in the source (or emitter) but you could also try sensing in the drain (or collector).  What this does is it reduces the voltage gain of the transistor to less than 1 and makes it easier to stabilize.  This is the most likely to work as you need with a more general type of load.

What you should probably do is start with a bipolar transistor and go from there.  Once you get it working if you really think you need a MOSFET then switch to that and rework the design a little.  In that case you should really use the source terminal as the output though not the drain as mentioned above.

Opamps driving mosfets to form a dynamic load is nothing new and not that difficult if you are not aiming for very high control bandwidth. Numerous commercial MOSFET-based programmable loads offer dynamic loading function with programmable slew rate, usually in the range of few A per us. They don't oscillate even if the DUT is connected with meter-long cables.

Im not sure why you stated all that.  I never said you cant do it, just that you have to do it right.

[TopQuark]

Im not sure why you stated all that.  I never said you cant do it, just that you have to do it right.

I agree I was not very specific. I meant to say the circuit configuration shown by the OP was tried and true, only requiring tuning to make it work, but I predict the modifications you proposed to be problematic. I believe it will cause more stability issues, if it works at all, certainly not what I would call "right".

Hello there,

Not sure what you mean, the original circuit is not a source follower.  The sense resistor is in the source circuit not the load.  To be a source follower, it has to have the load in the source circuit not the drain, and the drain would be connected to +Vcc.
See the following diagram.

In this new diagram, the load is connected to the source and the sense resistor is connected in series with the load.  That's the simpler connection but then the load can not connect to ground.  To get the load to connect to ground, the sense resistor has to be connected to the source and the load connected to the sense resistor and ground, or else the sense resistor has to be moved to be in series with the drain, but either way then the circuit has to be modified so that the op amp can still sense the current in the sense resistor which means a few more modifications to how the inverting and non inverting inputs connect to the sense resistor.

Also, C2 may have to be increased to 0.01uf or something.

The problem with the original circuit is that there are all kinds of conditions that can come up that will cause oscillation.  It works for some loads and not for other loads.  Even the best circuits can have problems like this, but that is probably one of the worst.

1. The OP is trying to build a DC load, a device that presents itself as a load, that sinks a set amount of current from a power source. Your circuit describes a programmable current source, that sources a set amount of current into a load.

2. Putting that very fundamental issue aside and lets assume we are trying to build a current source. In the circuit you propose, say you wish to source 1A through a simple 10 Ohm load, the gate voltage at the opamp output relative to ground that is needed to turn on the MOSFET is:

Vgs (Vgs thresh is 2-4V according to IRFZ44N datasheet, let's be charitable and say only 3V is needed for 1A Ids) +
V_load (1A x 10Ohm = 10V) +
V_shunt (1A * 0.1Ohm = 0.1V) = 13.1V

The original circuit is stated to be powered by a 9V battery. The LM324 output can swing from ground to V+ - 1.5V, which is 7.5V, not anywhere close to ~13V needed. So the proposed circuit fails to perform as a half decent current source.

As a load, the original circuit's opamp output voltage range only needs to cover Vgs required to turn the FET on + V_shunt. 7.5V at the gate will have no trouble sinking around ten amps, and max DUT source voltage is only limited by MOSFET Vds. With proper heatsinking and a tuned control loop, this can be a versatile general purpose device.

3. In the proposed modification, your opamp output includes Vgs and V_load. We all agree it can be tricky enough to drive Vgs to maintain current control stability, but now it has to account for Z_load as well. By simply hooking up different resistors as a load will change your control loop gain (V_gate / I_mosfet), making it very difficult to tune for stability, not to mention if you stick a cap or inductor in there. Including a wildcard impedance inside your control loop is just inviting problems.

[temperance]

@ exe, well done.

@ Kane
A fast responding dummy load which doesn't oscillate with jelly bean components. The disadvantage being the quiescent current in the totem pole buffer stage and the current trough R2. In total something like 5...7mA.
-D4 and D5 make sure that the input of the buffer stage can be driven to GND.
-C2 assists on "eating" the current injected trough drain gate capacitance if a transient appears on the drain.
-C1 and R5 compensate parasitic inductance introduced by the cables connected to the drain. C1 is a film capacitor, any type, nothing fancy. R2 must be a 1..3W resistor depending on the input signal.
-Q1 and Q1: any "normal" transistor will do. BC547, BC557...
-All small signal diodes: any small signal diode will do. 1N4148, 1N917, BAS318, BAV70,...
-The LT1014 is a low offset version of the LM324.

This is what those cheap Chinese dummy load circuits which you can buy everywhere for peanuts but don't work should look like.

[exe]

to temperance:

Does it make sense to split R1 into two resistors (one for Q1's emitter and one for Q2's emmitter)? Otherwise I think gate pull-up will be slower than pull down. Or this is intended? Like here on Figure 6A: https://sound-au.com/amp_design.htm#s22

[MrAl]

Im not sure why you stated all that.  I never said you cant do it, just that you have to do it right.

I agree I was not very specific. I meant to say the circuit configuration shown by the OP was tried and true, only requiring tuning to make it work, but I predict the modifications you proposed to be problematic. I believe it will cause more stability issues, if it works at all, certainly not what I would call "right".

Hello there,

Not sure what you mean, the original circuit is not a source follower.  The sense resistor is in the source circuit not the load.  To be a source follower, it has to have the load in the source circuit not the drain, and the drain would be connected to +Vcc.
See the following diagram.

In this new diagram, the load is connected to the source and the sense resistor is connected in series with the load.  That's the simpler connection but then the load can not connect to ground.  To get the load to connect to ground, the sense resistor has to be connected to the source and the load connected to the sense resistor and ground, or else the sense resistor has to be moved to be in series with the drain, but either way then the circuit has to be modified so that the op amp can still sense the current in the sense resistor which means a few more modifications to how the inverting and non inverting inputs connect to the sense resistor.

Also, C2 may have to be increased to 0.01uf or something.

The problem with the original circuit is that there are all kinds of conditions that can come up that will cause oscillation.  It works for some loads and not for other loads.  Even the best circuits can have problems like this, but that is probably one of the worst.

1. The OP is trying to build a DC load, a device that presents itself as a load, that sinks a set amount of current from a power source. Your circuit describes a programmable current source, that sources a set amount of current into a load.

2. Putting that very fundamental issue aside and lets assume we are trying to build a current source. In the circuit you propose, say you wish to source 1A through a simple 10 Ohm load, the gate voltage at the opamp output relative to ground that is needed to turn on the MOSFET is:

Vgs (Vgs thresh is 2-4V according to IRFZ44N datasheet, let's be charitable and say only 3V is needed for 1A Ids) +
V_load (1A x 10Ohm = 10V) +
V_shunt (1A * 0.1Ohm = 0.1V) = 13.1V

The original circuit is stated to be powered by a 9V battery. The LM324 output can swing from ground to V+ - 1.5V, which is 7.5V, not anywhere close to ~13V needed. So the proposed circuit fails to perform as a half decent current source.

As a load, the original circuit's opamp output voltage range only needs to cover Vgs required to turn the FET on + V_shunt. 7.5V at the gate will have no trouble sinking around ten amps, and max DUT source voltage is only limited by MOSFET Vds. With proper heatsinking and a tuned control loop, this can be a versatile general purpose device.

3. In the proposed modification, your opamp output includes Vgs and V_load. We all agree it can be tricky enough to drive Vgs to maintain current control stability, but now it has to account for Z_load as well. By simply hooking up different resistors as a load will change your control loop gain (V_gate / I_mosfet), making it very difficult to tune for stability, not to mention if you stick a cap or inductor in there. Including a wildcard impedance inside your control loop is just inviting problems.

It's an example of a source follower.  Have you never seen a source follower before?
If you have doubts do a simulation, but i suggest a bipolar not a mosfet.  Any of these circuits may need compensation of some type though.
Of course if you want an actual current sink, that's different.  The example is for providing current to some load, as in powering it.

[temperance]

Hello MrAl,

maybe we can agree on a few things?

-The original circuit is for a current sink. Not a current source.
-Whatever name the circuit in question has, for the op amp the gain of the buffer is always <1. The remainder is a matter of text book definitions which more often then not are open for interpretation and unfortunately misunderstandings.


Thank you.

[MrAl]

Hello MrAl,

maybe we can agree on a few things?

-The original circuit is for a current sink. Not a current source.
-Whatever name the circuit in question has, for the op amp the gain of the buffer is always <1. The remainder is a matter of text book definitions which more often then not are open for interpretation and unfortunately misunderstandings.


Thank you.

Hi,

Sure, no problem.  I was trying to show an example.
Here is an example that should be more to your liking.

Note the load is in the emitter circuit (R3) and the sense resistor is R1.  Vo1 is just for testing.
You should be able to use a Darlington if you need higher current.

[exe]

Here is an example

I'm curious why using PNP bjt? Wouldn't NPN be more stable bc it's an emitter follower? What's the purpose of base resistor?

[temperance]

All good. Reading what you wrote earlier, it seems there is a misunderstanding in your circuit analysis. A quote from something you've posted earlier:

That's the way it is with these circuits because the transistor provides an increase in loop again, and it could be a lot, and that means the internal compensation of the op amp is no longer effective in keeping the circuit stable.  This i could guess is the major problem.

The MOSFET or transistor, has a gain <1. It's the voltage across the source resistor which is being fed back into the op amp. The only thing the buffer does is providing current gain (hopefully a lot) which doesn't change the loop gain at all in this case.

For the voltage across the resistor (R3 in the circuit I posted) we get: A= Vin/Vout= (Gm x Rs)/ (1+ Gm x Rs). So, no matter what Gm is and Rs might be, the gain is very close to 1 but never >1. And that's what the inverting input of the op amp is being fed with. What remains is getting rid of the pole pole introduced by the MOSFET capacitance and it's driving source.

Also, TopQuark does know what his talking about.

[temperance]

@ exe

Does it make sense to split R1 into two resistors (one for Q1's emitter and one for Q2's emmitter)? Otherwise I think gate pull-up will be slower than pull down. Or this is intended? Like here on Figure 6A: https://sound-au.com/amp_design.htm#s22

-No, during fast transient testing for example the driver must eat the current injected trough the drain gate capacitance when the drain voltage increases. The injected current will translate into a voltage across any emitter resistor added in series with Q2. Something you don't want. You want to gate voltage to remain unchanged during such events.

-The small asymmetry is not such a problem because the op amp slew rate is the limiting factor in both directions.

-I just noticed that the value I've chosen for R3 (by some ruff guess) seems a little high. 33R would be more appropriate for driving large capacitance MOSFET's. (of course, the op amp still doesn't require any compensation.)

And if you really like, you can omit one diode (D1 for example) and replace it with a trimmer to set the quiescent current in the totem pole stage to something like 5mA. Or the fancy stuff a Vbe multiplier. (not really required of course)

Why the quiescent current: for two reasons.
1. no cross over problems.
2. Q2 is now always readily biased to eat the injected current. Response time of the current sink with a BC807 or similar falls in the the range of 5ns. (If you ever want to make transistors switch very fast, use some biasing and avoid saturation. The numbers you will see in spice are darn close to a real circuit.)

[MrAl]

All good. Reading what you wrote earlier, it seems there is a misunderstanding in your circuit analysis. A quote from something you've posted earlier:

That's the way it is with these circuits because the transistor provides an increase in loop again, and it could be a lot, and that means the internal compensation of the op amp is no longer effective in keeping the circuit stable.  This i could guess is the major problem.

The MOSFET or transistor, has a gain <1. It's the voltage across the source resistor which is being fed back into the op amp. The only thing the buffer does is providing current gain (hopefully a lot) which doesn't change the loop gain at all in this case.

For the voltage across the resistor (R3 in the circuit I posted) we get: A= Vin/Vout= (Gm x Rs)/ (1+ Gm x Rs). So, no matter what Gm is and Rs might be, the gain is very close to 1 but never >1. And that's what the inverting input of the op amp is being fed with. What remains is getting rid of the pole pole introduced by the MOSFET capacitance and it's driving source.

Also, TopQuark does know what his talking about.

Hello again,

Not sure why you are harping on this when i posted a better circuit diagram that you apparently ignored.

There's more to it than that.  That appears to be what you and your friend seem to be overlooking.
If it was that simple, then why did it not work for you the first time and why so many posts talking about such a "simple" concept.
Almost 40 posts now.  Gee what a simple thing to do, let's create a mosfet current sink and then figure out why it doesnt work over multiple posts (chuckle) and at the same time still say it's simple.  BTW i like to add a little levity now and then to keep the discussion a bit lighter in spirit.

It's time to put your simulator where your mouth is (ha ha).
Simulate a circuit you think will work, then post here.  It's time for proof, not words alone.
See, i can say a rock and a racoon will form the best current sink (har har).  See how easy that was?  It's only when we prove it.

It may be that a mosfet circuit will in fact work one way or another, but the way it appeared in the first diagram in this post will not be as stable as a real common source circuit.  That's because the transistor adds GAIN.  Apparently it is gain that you dont seem to see is there.
That's ok i guess, but you should look at what happens in the drain when the transistor drives the mosfet.

As i said you may get it to work, but then get it to work and stop knocking other designs when you still havent gotten one to work, and also you should go back and compare the circuits and see what one is the MOST stable.
Notice that there has been a lot of rocket testing recently, and many of the projects have failed (not all though).  Why is that.  It's because the designers believed it would work but it didn't in actual practice.
Where did the Space Shuttle go.  It took years to figure out it was not as practical as thought.
Elon Musk is a pretty smart mofo, yet he has had many failures.  Testing and proving, that's what it is all about in the real world.

If you want the MOST stable circuit, then you go with the most stable design.  That's why i am trying to point out to you.
I am not forcing you to use any particular circuit you are certainly free to use any design you care to.  Im just suggesting a better circuit and it comes from some 50 years experience, not only in general electronic analysis and professional design work with companies and universities, but in power supply design, very sophisticated power supply design that involved not only these simple DC supplies but also in pure sine converters that had to be very low in THD and also very high in efficiency (90 percent plus).
What i am trying to do is share those years of work and study and with my huge technical library with you so you can get a good working circuit.  It's always, always up to you if you want to use a given design or any given advice but now you know where this is coming from.

[MarkF]

Some reference material from the forum:

   Jay_Diddy_B's Electronic Load with analysis.

   My Dummy Load which can be externally driven up to a few kHz.

   Peter Oak's discussion on stability. 

I found that the feedback capacitor must be at least 5nF to stop oscillation. 
I would reduce R5 <= 100Ω and R6 <= 10KΩ in the original post circuit.

[temperance]

@ MarkF

did you read what other people posted. Especially what I posted? Probably not, adding more clutter to the discussion.

-If you would read what I wrote, you might understand why a feedback capacitor of 5nF would be required. And what is 5nF without stating the feedback resistor value? A Useless commend so far.
-Your dummy load is faulty.
-The video's shows an other faulty dummy load. On top of that, sponsored by Farnell. Well done farnell for trying to be an educator spreading faulty circuits. Put a transient on the drain and see what happens. In the second video he seems be toying around with speed up capacitors to mitigate the original fault, undoing the compensation. Which of course doesn't help.

My posts took the guesswork out of compensating a dummy load. Just like Jay_Diddy_B did. Build it, try it. Sit back and enjoy a properly compensated feedback circuit running at speeds you can't achieve with guesswork and a transient response beyond your imagination with nothing else than jelly bean components which can be driven op to 10KHz and even more if you replace the op amp.

So, maybe instead of posting more clutter you might want to read what has been written en discuss how to compensate the loop properly (yes, there is room for improvement). Instead you add in your mall functioning experience. That math involved isn't complicated at all in this simple circuit.

@ MrAI:

Not sure why you are harping on this when i posted a better circuit diagram that you apparently ignored.

It's time to put your simulator where your mouth is (ha ha).

ok, I give up. Even with the math in front of you, you keep on saying that the gain is >1. The conclusion you should draw from what I wrote is that you're better circuit is an attempt to improve something you didn't understand.

And no, this is not only a simulator. I used LT spice to quickly draw a schematic. Build it, try it.

[temperance]

ok, MrAl, you asked for it.

What you see:

-the circuit as attached earlier with R3 changed into 33R.

-Voltage measured across 0.1R sense resistor. 1kHz test signal.
-Rise and fall time measured across the 0.1R sense resistor.

As you can see, this thing is stable no matter what and extremely fast too. Just for fun, it easely handles 10kHz as shown below. This is not the fastest dummy load featured an EEVBLOG. But the the fastest one featuring jelly been components.

The ringing seen is not the dummy load but the GND connection. The wire inductance is ringing because of the high di/dt.

Your 50 years experience, which is a bad argument anyhow, down the drain... 24 years experience in action.

The only "problem" encountered is the quiescent current setting of the totem stage. 1 diode must be removed and replaced with a trimpot or something.

[MrAl]

ok, MrAl, you asked for it.

What you see:

-the circuit as attached earlier with R3 changed into 33R.

-Voltage measured across 0.1R sense resistor. 1kHz test signal.
-Rise and fall time measured across the 0.1R sense resistor.

As you can see, this thing is stable no matter what and extremely fast too. Just for fun, it easely handles 10kHz as shown below. This is not the fastest dummy load featured an EEVBLOG. But the the fastest one featuring jelly been components.

The ringing seen is not the dummy load but the GND connection. The wire inductance is ringing because of the high di/dt.

Your 50 years experience, which is a bad argument anyhow, down the drain... 24 years experience in action.

The only "problem" encountered is the quiescent current setting of the totem stage. 1 diode must be removed and replaced with a trimpot or something.

First, when you say "50 years experience is 'down the drain' " that just tells me you still dont understand the situation and that you have very poor social skills if you can actually tell that to someone that is trying to help you, EVEN IF YOU ARE RIGHT.

Second, since you are so sure of your circuit, then why not just go with it.  Use the circuit you have and be happy with it.

Third, and last, i should point out that 'math' is not reality.  Math is an artificial rendering of reality, and if even one little assumption is wrong we get a big fat pile of BS.  If you really want a detailed map of what is happening, then do a root locus analysis, but be sure to include the MOSFET parameters.

So with that, i wish you good luck with your newfound 'success' 

[temperance]

First, when you say "50 years experience is 'down the drain' " that just tells me you still dont understand the situation

Why are you so sure about yourself? Attached is a circuit diagram with two buffered op amps. Which one of the two buffers, according to you, is is not an emitter follower. What is the voltage gain of both buffers according to you if you ignore the op amp?

About my poor social skills: read what you wrote yourself. I rarely ridicule others unless being asked for. Remember how you wrote a wall of text ridiculing my schematic, insinuating I just simulated something and don't know how to build a real circuit,... on and closing the sentence with something like haha?

And if I find time, I will build your circuit and prove you that are completely wrong if I'm not too busy. Or do it yourself and prove me wrong? Your welcome.

[MrAl]

First, when you say "50 years experience is 'down the drain' " that just tells me you still dont understand the situation

Why are you so sure about yourself? Attached is a circuit diagram with two buffered op amps. Which one of the two buffers, according to you, is is not an emitter follower. What is the voltage gain of both buffers according to you if you ignore the op amp?

About my poor social skills: read what you wrote yourself. I rarely ridicule others unless being asked for. Remember how you wrote a wall of text ridiculing my schematic, insinuating I just simulated something and don't know how to build a real circuit,... on and closing the sentence with something like haha?

And if I find time, I will build your circuit and prove you that are completely wrong if I'm not too busy. Or do it yourself and prove me wrong? Your welcome.

Hello again,

Oh i see you took my improvement suggestions to heart i was not intending that.
See, when people try to help sometimes it sounds like they are being overly critical, and that's a shame.  It may have sounded that way but it was intended just to help and draw out some of the pitfalls of various schemes, those that are the same as the circuit you need and those that are similar (like the current source).

What happens with the mosfet is the gain of the mosfet itself comes into play because of various things about the speed of the mosfet and the speed of the op amp, comparatively.  The mosfet responds fast while the op amp is rather slow.  When the mosfet is 'told' to put out more current, it will keep raising the current for a period of time which there is no control over.  That causes an overshoot.  It takes time for the op amp to detect this and correct the gate drive, but meanwhile the mosfet it still putting out a current that is too high.  It may dampen out, that's a hope.

What you can do is simple i think.  Just use spice to simulate the following two circuits and then try to determine which one is more stable.
There's a third circuit i didnt get time to draw but these two may act as a reference.

BTW this problem comes up in other places too but sometimes it's even worse, like with the LM431 which requires a certain output capacitance to remain stable.

My original concern though was what happens if you use something other than a resistive load.

Im posting the two circuits, and note there is no compensation capacitors.  Look at the outputs of both circuits and see what you think.
The two are easy to set up in a spice program.

[Avelino Sampaio]

What happens with the mosfet is the gain of the mosfet itself comes into play because of various things about the speed of the mosfet and the speed of the op amp, comparatively.  The mosfet responds fast while the op amp is rather slow.  When the mosfet is 'told' to put out more current, it will keep raising the current for a period of time which there is no control over.  That causes an overshoot.  It takes time for the op amp to detect this and correct the gate drive, but meanwhile the mosfet it still putting out a current that is too high.  It may dampen out, that's a hope.

Depending on the design, it is possible to slow down the Mosfet response, bending the edges of the signal.

For example, in a PSU transient test, using a maximum load of 2A and a signal with a rising edge of 8µs and considering the use of the mosfet (IRFP260) used by Temperance, which has a Qgs of 39nC, we have a maximum current estimated 4.8mA:

Imax = Qgs/dt
Imax = 39nC/8µs =~4.8mA

My conclusion is that the direct use of an Opamp to drive the IRFP260 is plausible, even with a 50µs pulse. Generally a 200µs pusl is sufficient for a good transient test.

[RoGeorge]

There is also the Cgd, which seems 2-3 times bigger than Qgs (110nC vs. 42nC in https://www.vishay.com/docs/91215/irfp260.pdf).

When the load is connected in the drain, it means the voltage on the drain will swing in the opposite direction than the swing of the gate terminal, which makes the voltage on the Cgd to appear steeper than it would be in a common drain repeater.  This extra voltage swing of the drain terminal (when the transistor is not working as a source repeater) will need more current at the gate (to remove the gate charge).  A common-source (load placed at the drain side) will make the gate current to depend more of the load's impedance (because the load's impedance gives the voltage slope at the drain) than it will depend for a common-drain voltage repeater (load placed at the source side).

This makes me believe the gate current will need to be higher in the common-source configuration than in the common-drain configuration, so it would be preferable to have the load on the source side, but I didn't double check this kind of argument in simulation/practice.

[Avelino Sampaio]

There is also the Cgd, which seems 2-3 times bigger than Qgs (110nC vs. 42nC in https://www.vishay.com/docs/91215/irfp260.pdf).

When the load is connected in the drain, it means the voltage on the drain will swing in the opposite direction than the swing of the gate terminal, which makes the voltage on the Cgd to appear steeper than it would be in a common drain repeater.  This extra voltage swing of the drain terminal (when the transistor is not working as a source repeater) will need more current at the gate (to remove the gate charge).  A common-source (load placed at the drain side) will make the gate current to depend more of the load's impedance (because the load's impedance gives the voltage slope at the drain) than it will depend for a common-drain voltage repeater (load placed at the source side).

This makes me believe the gate current will need to be higher in the common-source configuration than in the common-drain configuration, so it would be preferable to have the load on the source side, but I didn't double check this kind of argument in simulation/practice.

In the transient test of a PSU, the drain voltage variation is very small (maximum of about 200mVpp). The gate voltage orbits around 4.5v. The Mosfet in this case always works in the linear region.  For Cgd to have any influence, and I consider it little, the PSU output must be below 4.0v.

[exe]

In the transient test of a PSU, the drain voltage variation is very small (maximum of about 200mVpp). The gate voltage orbits around 4.5v. The Mosfet in this case always works in the linear region.  For Cgd to have any influence, and I consider it little, the PSU output must be below 4.0v.

That's an interesting discussion. Anybody willing to do a spice simulation?)

In my limited experience, drawing more than a milliamp or two reduces opamp bandwidth. So, I prefer to do sziklai/darlington, that improves transient response. The question is how fast it needs to be. Too much bandwidth won't do good for a general-purpose power supply with long leads and "difficult" load.