Confused by negative gate voltage for JFETs

[hurricanehenry]

Hi - I understand basically how BJTs and JFETs work. But don't quite understand how you get negative voltage on the JFET gate.

For the BJT I understand it's current driven, and you are enabling carrier flow between emitter and collector when you put in a current through the base.

For the JFET, I understand it's voltage driven, and when you put in a negative voltage to the gate on an N-channel JFET, it will create more of the depletion region and constrict the carrier flow across the channel between source and drain.

HOWEVER I don't quite understand how on earth (no pun intended) you get negative voltage at the gate, if you are grounding the source, and the drain is positive.

I know you bias both the BJT and the FET to the q-point, using voltage divider resistors, but:

How does the gate get even more negative, with respect to ground (wrt to the source), in a DC circuit?

And if the signal to be amplified comes through AC (which it should), then how do you ground the source, wrt the AC signal?

I'm really stuck on this bit, any help appreciated.

[tatus1969]

to run a JFET you typically use bipolar supply rails, these provide you with negative bias. If the source is tied to ground as in your example, this is the simplest way to do this. AC coupling can be done with a (high ohmic) resistive divider that provides suitable negative bias, and you use a capacitor to couple your input signal.

[uncle_bob]

Hi - I understand basically how BJTs and JFETs work. But don't quite understand how you get negative voltage on the JFET gate.

For the BJT I understand it's current driven, and you are enabling carrier flow between emitter and collector when you put in a current through the base.

For the JFET, I understand it's voltage driven, and when you put in a negative voltage to the gate on an N-channel JFET, it will create more of the depletion region and constrict the carrier flow across the channel between source and drain.

HOWEVER I don't quite understand how on earth (no pun intended) you get negative voltage at the gate, if you are grounding the source, and the drain is positive.

I know you bias both the BJT and the FET to the q-point, using voltage divider resistors, but:

How does the gate get even more negative, with respect to ground (wrt to the source), in a DC circuit?

And if the signal to be amplified comes through AC (which it should), then how do you ground the source, wrt the AC signal?

I'm really stuck on this bit, any help appreciated.

Hi

For a circuit that is *practical* in terms of biasing an NPN or a JFET, you will have resistance between ground and the device. The voltage drop on that resistor is what raises the device above ground. It keeps you in the linear region and stabilizes the bias current over temperature and device variations.

Bob

[hurricanehenry]

Sorry I’m not really getting what you guys just posted.

Perhaps let me rephrase my question.

So you have a positive voltage at the drain, say 5 volts or whatever.

Now, the source is at 0 volts, grounded.

With the gate, anything above 0 volts is useless.

You need to get the gate to maybe -1 volts to start constricting the N-channel, and maybe -4 volts to completely cut it off.

So, how do you get the gate to be less than the 0 volts that the source is at? The gate has to be referenced to both the source and drain voltages, right, otherwise it is sort of floating and undefined with respect to the S and D voltages.

Thanks.

[kg4arn]

To get the jet to self bias, you use a resistor between source and ground.
The source current raises the source pin voltage above ground.
With the gate grounded, the gate is more negative than the source and the bias stabilizes in the active region.

[T3sl4co1l]

Voltages can be below ground.

Ground is just a convention, a point of view.  Connect a battery backwards ("+" to ground) and its other terminal will be negative.

Voltage itself is nothing but a difference.  It is completely meaningless to speak of "a voltage" in a circuit.  Voltages are necessarily measured between two points.  Because we're lazy, we normally designate one node as default.  This is ground.

You could just as well ground the gate (because, who says the source must be grounded, anyway?!) and drive the source.  The source, of course ( ), carries the same current as the drain, which might not be very convenient (it presents quite a burden to your signal input!), but as it happens, you get voltage gain all the same (well, for a reasonably sized load on the drain terminal).  In this case, to achieve negative gate bias, you positive-bias the source pin.  Weird?  Nah, the JFET's only got three terminals, it doesn't know any better -- how could it?

Tim

[hurricanehenry]

Ok thanks everyone. I got it now.

I kept thinking that the Source was just a dead short to ground (0 volts) but actually you set the Source voltage (above 0 volts) using a resistor, then THAT level becomes the "logical ground" for the whole JFET, and you can then set the Gate to below that "logical ground" which is still above 0 volts, but with sufficient leeway to do the AC amplification. And with the Drain, that is way above the voltage level of the Source.

So everything is above 0 volts, but with respect to the Source, the Gate is negative, and the Drain is positive.

Let me know if I got this wrong. I think I got it though?

[T3sl4co1l]

Ok thanks everyone. I got it now.

I kept thinking that the Source was just a dead short to ground (0 volts) but actually you set the Source voltage (above 0 volts) using a resistor, then THAT level becomes the "logical ground" for the whole JFET, and you can then set the Gate to below that "logical ground" which is still above 0 volts, but with sufficient leeway to do the AC amplification. And with the Drain, that is way above the voltage level of the Source.

So everything is above 0 volts, but with respect to the Source, the Gate is negative, and the Drain is positive.

Let me know if I got this wrong. I think I got it though?

Bingo.

Tim