Hi, not bad at all for a first PCB design. Just few recomendations:
- If you are building relliable device, size shouldn't matter. Don't beat yourself to get it on 10x10cm board, while you may miss some important things.
![Wink ;)](https://www.eevblog.com/forum/Smileys/default/wink.gif)
- You should never route capacitors on separate route from where the main current flows. F.e. the route from rectifier to C2 is added serial resistor (and inductor), which is actively increasing your ESR. The same thing for C3 (even worse case). For some bigger current impuls, its like if it's not there at all.
- Make sure that you know which part of design does what. You've done quitte a good job with that sensing (R27 and R34) and connection of grounds.
- Keep feedback loops as short as possible (f.e. R6, C6 is IMHO OK).
- Make sure that you block the supply voltage for OAMPS. Blocking caps are often not in the schematic (!), I see that you've added C40-43. One cap between U1 and U3 (on +12V and -12V) shouldn't hurt
![Smiley :)](https://www.eevblog.com/forum/Smileys/default/smiley.gif)
. You can also add some caps at those power lines (f.e. near R3, R43), same thing
![Smiley :)](https://www.eevblog.com/forum/Smileys/default/smiley.gif)
- It usually looks better if you use like 3 or 4 different widths of routes only (you've done that).
- Even tho devices like MOS-Fets have (in stable mode) no current flowing into gate, keep in mind that you have to charge/discharge the cappacity of that gate. I would personaly use wider routes from R39, R38, R45/C22, R44/c23 and Q2, R3. You have a lot of space there, so why not use it. Btw placing R3 is good solution since it has current path to Q2 and voltage path to the resistors at gates. I would maybe took the -12V for Q2 from a separated route than from OAMPS, but i don't think it's critical.
- Voltage sources are usually made in line, I get that you wanted to have J4 and J1 on the same side and to save space, but if you think where the main current flows, there is one big open loop (rectifier, fets, R35/36, R2). Those power routes should be close together (essentially the same way you've done +12V and -12V).