Hi Fellow Nerds,
I'm designing a CPU card using an HD63C09P which has a 16-bit address bus, but I want to use a massive 512KB SRAM (KM684000BLP-7) and also a 512KB ROM (TMS27C040-15JL).
I think I want to segment 6309's 64KB address space into 8 pages of 8KB each, and have a way to remap any of these pages to anywhere within ROM or RAM. I also want a small area be IO-space and be either relocatable or at least capable of being turned on or off in the memory map, and if this space could contain some memory mapped-registers for bank selection, I think that would be great. The 6309's interrupt vector table is at 0xFFF0...0xFFFF, so the last page should be mapped to ROM initially, but it would be nice to be able to later remap this page to RAM so the vectors could be reconfigured.
I have a bunch of little ATF16V8 PALs in DIP-20 packs, but I don't yet know much about them. Would one or more of these be up to the task? It seems like I need to implement some extra address lines and chip selects, (A16, A17, A18... /CSROM, /CSRAM...) How would I interact with the PAL's to select banks? Could they look like memory-mapped registers, or would they be invisible and respond to some type of magic reads or writes or some such? I'm hoping for something performant so banks can be switched using as few instruction cycles as possible,
Would it make more sense to use a bigger CPLD for this? (I have an ATF2500C in a DIP-40), or a peripheral controller like a VIA, CIA, PIA, or even an FPGA? I guess having a 512KB SRAM on board already blew any prospects of the thing being period-correct anyway.
Attached is the schematic so far, minus glue logic, power-on-reset generator, bus pinout, etc.
Geek on,
Craig