Circuit to measure N-channel JFET’s Vgs(off)

[Sifunkle]

Hi all,

I’ve been lurking for a while, but actually spending some time with a breadboard (rather than just reading about circuits and components) has prompted me to join and post. It’s probably too late for anyone to save my sanity, but if anyone cares to attempt salvage, read on.

I’m trying to learn how to work with JFETs. Thought I’d mostly understood the basics but am frustrated that the attached circuit is not behaving as hoped for (please excuse the smudges and rank amateurishness of diagram). I was hoping to use the circuit to measure the Vgs(off) of a few N-channel JFETs, by using the potentiometer to sweep away from the reference/ground (i.e. towards lug 3 on my diagram) until the ammeter just reads zero, then taking Vgs(off) from the voltmeter.



Unfortunately, while the ammeter will vary with the potentiometer, it never gets particularly close to zero. (The measured current also seems lowest in the middle of the pot’s sweep too, which I thought was odd. I’m using a 5K linear taper pot, if that matters.)

The left-hand battery has a voltage wide enough to encapsulate the datasheet’s range for Vgs(off). The right-hand battery is approximately triple the voltage of the left. I have also tried including a drain resistor and a source resistor, without any particular change.

Any thoughts? Feel free to drop a litany of all the stupid mistakes I’ve made. Thanks in advance!

(Can’t for the life of me get my image to show in preview; hoping it does in actual post…)
(Several edits later: success. Success that was not reflected in Preview mode…)

[magic]

What sort of voltages and currents are we talking about? Any chance that you are measuring leakage through the gate-drain junction?

BTW, as a quick and crude measurement circuit I would try this:
gate: ground
drain: 9V battery
source: DMM with 10MΩ input impedance, the other probe grounded

The DMM shows Vgs at source current equal to Vgs/10MΩ, or a fraction of μA. This should be close to the datasheet spec, I think.

[Kleinstein]

The circuit may damage the JFET from too much power. The voltage for the drain should be relatively low, like 3 V to avoid thermal problems, at least with most parts. In rare cases even the current may get a bit high, though most JFETs can withstand Idss.

A possibility to get add readings is when the circuit oscillates, e.g. with inductive coupling and parasitic inductance.

[Zero999]

There isn't enough infomation.

What are the voltages?
Part number?

[Sifunkle]

Thanks for the replies!

What sort of voltages and currents are we talking about? Any chance that you are measuring leakage through the gate-drain junction?

On the latter, I’m unsure how to tell, but hopefully not as I was getting Id on the ammeter around 2/3 of Idss. I understand your quick test circuit and will give it a go!

The circuit may damage the JFET from too much power.

Admittedly I didn’t do exact calculations, but stayed well within supply I’ve seen in marketed circuits using the same FET. And I was only closing the circuit just long enough to take measurements, which hopefully helped with power/thermal considerations. I’ll add coupled and parasitic inductances to my reading list (alongside similar for capacitances)!

There isn't enough infomation. What are the voltages? Part number?

Sure, I’m playing with this 2N5484 https://www.interfet.com/jfet-datasheets/jfet-2n5484-2n5485-2n5486-interfet.pdf
I initially used a 9V battery to supply the drain and a 6V one for the gate, but then decided to try and match the datasheet’s test condition Vds by putting a few partly-used 9V in series to equal approximately 15V.

Sorry I omitted the info to begin with. As someone wanting to learn, I’ve found it more useful to talk ‘algebraically’ than use exact values, but then I’ll also be ignorant as to when it’s too hard to do the former and the latter are needed.

[Zero999]

There is a way to do this with only one power supply.

Connect the gate to 0V and the potentiometer to the source. Now you have a common gate amplifier.

Here's a practical schematic.


A simulation. LTSpice doesn't have a potentiometer model, so it's represented by Pot1a and Pot1b.
V(s) is the source voltage.
Id(J1) is the drain current.
The horizontal axis 10m to 910m, 0.01 to 0.91 is the position of the potentiometer wiper, with 0 being one end and 1 the other.

[Sifunkle]

There is a way to do this with only one power supply… Here's a practical schematic.

I believe I understand this circuit - if I’m not wrong, the simulation shows Vgs(off) as 1.35V, occurring where Id(J1) reaches zero at 160m on the horizontal axis.

Well… I breadboarded the circuit to test my first JFET and adjusting the potentiometer did not alter Id at all (which hovered around 0.35-0.45mA). I could see Vgs changing, but not as anticipated for the 9V supply: the 5k potentiometer only swept Vgs from 0V to around -0.75V. I tried a 100k pot - did not anticipate anything would change, so at least I was vindicated on one front.

I continuity checked all components (other than the JFET) and verified correct function. I tried a different 2N5484 (#2 of the 6 I ordered) - same result. (Until that point, I’d only played with the one component just so I’d have several spare in case my naivete broke the first one.)

BTW, as a quick and crude measurement circuit I would try this:
gate: ground
drain: 9V battery
source: DMM with 10MΩ input impedance, the other probe grounded

Tried this on the breadboard too. Zero voltage detected with 10M input impedance DMM connected as described (well, occasional microvolt waver, but nothing beyond what I get waving the probes around randomly in the air).

  Can I learn anything from this? (Ideally something more hopeful than ‘Don’t trust whoever sold you the JFETs’.)

[iMo]

..LTSpice doesn't have a potentiometer model, so it's represented by Pot1a and Pot1b.

You should have downloaded some libs (ie. like Bordodynov's library package) and you get it, works fine, the "wiper/T" is from 0.0 to 1.0 and could be used as a parameter as well..

http://bordodynov.ltwiki.org/

He is active on the https://groups.io/g/LTspice/ as well..

[Zero999]

..LTSpice doesn't have a potentiometer model, so it's represented by Pot1a and Pot1b.

You should have downloaded some libs (ie. like Bordodynov's library package) and you get it, works fine, the "wiper/T" is from 0.0 to 1.0 and could be used as a parameter as well..

http://bordodynov.ltwiki.org/

He is active on the https://groups.io/g/LTspice/ as well..

I already have a potentiometer library, but LTSpice has no way of embedding symbols into the .asc file, so I would have to put it all in a zip file, which is more effort and many people will be concerned about the security risk, so I don't bother. It's much easier to use two separate resistors.

I made a thread about this a few years ago.
https://www.eevblog.com/forum/beginners/simulating-potentiometers-using-ltspice

There is a way to do this with only one power supply… Here's a practical schematic.

I believe I understand this circuit - if I’m not wrong, the simulation shows Vgs(off) as 1.35V, occurring where Id(J1) reaches zero at 160m on the horizontal axis.

Well… I breadboarded the circuit to test my first JFET and adjusting the potentiometer did not alter Id at all (which hovered around 0.35-0.45mA). I could see Vgs changing, but not as anticipated for the 9V supply: the 5k potentiometer only swept Vgs from 0V to around -0.75V. I tried a 100k pot - did not anticipate anything would change, so at least I was vindicated on one front.

I continuity checked all components (other than the JFET) and verified correct function. I tried a different 2N5484 (#2 of the 6 I ordered) - same result. (Until that point, I’d only played with the one component just so I’d have several spare in case my naivete broke the first one.)

Is it possible the J-FETs are fake?

Please post some pictures.

[magic]

Is it a TO92 device? Check if it isn't an ordinary BJT with false markings...

[Sifunkle]

I’m not too sure how to tell fakes, although a quick google found some comments about small, off-centre notch in top of package being suggestive, as you can see in the last photo…





Purchased from what is touted as a reputable supplier, not some random eBay seller.

[magic]

Start with testing for PN junctions between pins, this will tell which pin really is gate (or base) and what's the true polarity of the device (N-ch/NPN or P-ch/PNP).

Short the gate to source and see if you can measure channel resistance between source and drain. If this shows open circuit, it's probably an NPN. Connect an LED and resistor between collector and 5V, apply some base current with a resistor and watch the LED light up

(BTW, in such case the pin you originally thought was drain is probably the emitter and the other pin is the collector).

[Zero999]

All you need is a multimeter, ideally with a diode test function.

A J-FET looks like a resistor connected between the drain and source and the gate connected to the drain and source via diodes. The drain and source are interchangeable on most J-FETs.

In this case the resistor will probably be between 50 and a couple of hundred ohms. The SPICE model I have has a resistance of 131R. I don't have a real one to measure.

[ledtester]

All you need is a multimeter, ideally with a diode test function.

At 4:03 in this video is a demonstration of testing a JFET with a multimeter:

JFET Audio Switch Circuit - 2n5457 -- Gadget Reboot
https://youtu.be/UHr5t8oiy04?t=4m3s

[Sifunkle]

Thanks everyone - think I’ve figured the issue out: pinout is mirror image of that specified. Probably a beginner’s mistake (but at least I’m qualified to have made it).

Looks like all my JFETs are within spec. Just. All very close to the minimum spec. Idss is proving much harder to pin down than Vgs(off) now. Seems like results vary considerably with the measurement circuit used (having tried several now). I suppose I should trust the one closest to the datasheet’s test specifications (Vds = 15V, Vgs = 0V, pulsed), which at its most basic would surely be:

Gate to ground
Drain to 15V battery via DMM
Source to ground

Unfortunately when I tried that (presuming ‘pulsed’ meant to close the circuit just long enough for the DMM to respond with a reading) a good number of readings were below spec. My understanding of Idss definition is ‘maximum Id with Vgs = 0’, so I figured I should go the highest measurement from within a set of attempts per component, which put Idss just above minimum for all of them…

TL;DR - I think I’m sorted now, but if anyone wants to validate me I’d appreciate it

[magic]

The pinout diagram in the datasheet you linked is labeled "bottom view".
Could this be the problem?

[Kleinstein]

Idss depends somewhat on the drain-source voltage. With pulsed they mean to exclude the heating effect - the time for the DMM to read may already be on the long side for this. Self heating tends to reduce Idss, AFAIR some -0.5% per K as rule of thumb.
To get less heating effect one may test at a lower voltage, like 5 V and accept the slightly lower value expected at the resuced voltage.

It is quite common to get parts from the same batch and thus similar parameters. This can be anoying if one looks for a specific value closer than the specs, but it is also helpfull if one looks for a matched pair.

[Sifunkle]

The pinout diagram in the datasheet you linked is labeled "bottom view".
Could this be the problem?

I actually noticed that, but mine seem to function as if it was ‘top view’!

With pulsed they mean to exclude the heating effect - the time for the DMM to read may already be on the long side for this. Self heating tends to reduce Idss, AFAIR some -0.5% per K as rule of thumb.

That makes sense - I had noticed the Id gradually decreasing if I left the circuit closed longer, presumably from the heating effect.

Unfortunately I was aiming for specific parameters rather than a matched pair. It’s the closest JFET I could find to replace an obsolete component, but has a lower minimum Idss than the obsolete one, which is unfortunately what my ones are all measuring close to.

[Kleinstein]

The low threshold fets are nice for low frequency amplification and as a current limit. The slightly higher threshold ones are preferred for RF amplification (one gets less input capacitance) and sometimes switching.  It depends on the ciruit if it still works with the lower Idss ones. Depending on the ciruit the threshold voltage may be more important than Idss. Most JFET circuits are quite tolerant to variations in the threshold - they kind of have to as this parameter scatters. So the FETs may still work even with a lower Idss.  If choosen as a suitable replacement they should still have a comparable capacitance and gm at the operating current.

[magic]

The pinout diagram in the datasheet you linked is labeled "bottom view".
Could this be the problem?

I actually noticed that, but mine seem to function as if it was ‘top view’!

Sounds like it was "made in China", then. There is a whole spectrum of dodgy Chinese vendors who appear to produce obscure or obsolete semiconductors; actual silicon inside varies anywhere from "same pinout, meets basic specs" (but often not SOA in power transistors) through "wrong pinout or doesn't meet specs" down to "completely different device" such as 2N3904 masquerading as a JFET.