To give you an idea what a "modest" chip development project for an SOC circa 2005 entailed:
Project:
an SOC with
6 processor cores
24 channels of SERDES Inputs
24 channels of SERDES outputs
2 DIMM controllers
PCI express root complex
6 coherent cache modules
Staffing:
3 architects
10 validation engineers
6 logic designers (they also did synthesis, place & route, and global integration)
1 manager
External IP
DRAM controller
DRAM phy
SERDES blocks
PCIexpress controller/phy
PLL blocks
CAD tools:
RTL synthesis
Place & Route
DRC checkers
SPICE
Timing validation tools
Verilog simulation tools
Formal validation tools
Time on task: 18 months.
Total expenses ~$15M to 18M US. (not including the processor instruction set architecture license)
Of that about $2M was for CAD tools alone, and we got an extremely good price due to some relationships.
Another $1.5M was spent on the IP block buyouts.
FAB, mask, testing, and prototype lot fees amounted to about $2M.
And this didn't include the cost of office space, workstations, server rooms, system prototypes, and all the other things that go into supporting an engineering team. Nor did it include the system engineers (that made the big box with the wheels and fans and power supplies and cables) the software team (that made it all go) and the executive team (that raised the money, paid the bills, found the customers, closed the sales, and such).
And the intervening years have not made things much simpler or much cheaper. Tools cost money. People to fly them cost money. Other people's intellectual property costs money.
There are smaller SOC efforts, but not many with industrial markets -- this chip was going into a large computing system. And this was a small SOC effort -- as remote in scale from something like a Xeon as a wheel barrow is from a dump truck. A typical big-time large server chip will take hundreds of person-years to bring to market.
Others may have participated in different efforts that had smaller (or larger) budgets and costs, but this is a datapoint, and not far from typical. Academic projects are cheaper because
- They don't pay for labor
- They don't pay for CAD tools
- They don't generally pay industrial prices for IP licenses
- They probably don't spend as much in validation
In general, an ASIC doesn't really pay unless you're talking about enough sales to offset the NRE -- so if you are looking at an SOC, there better be lots more than $20M in likely revenue (like 5x more...) or you'll have trouble making a competetive business out of it. (If you doubt the 5x multiplier, talk to a finance person, or a bank, or a professional investor. BOM cost is but a small part of getting something out the door and making a profit.)
Small custom analog chips may be different, but NRE doesn't really scale that well with the size of the die. MOSIS and such are nice, but they don't do production. Eventually you need to contract with a FAB or an intermediary. (It will likely be an intermediary, as TSMC and others don't normally deal with small (say, less than $1B?) operations.
So, what is there to do? Over the past 30+ years I've seen several models:
- Use an off-the-shelf solution. Most applications can't justify the expense of custom solutions.
- Find a vendor that has something close to the requirement and negotiate a "special version." (This is a comon approach in SOC markets, and is often the reason for lots of variants for one product.)
- (For digital applications) Use an FPGA or other configurable solution. (This often works out well for product volumes up into the ~100K units range. Much depends on your ability to negotiate terms and prices with a vendor.
- Contract custom development to a design services organization. This can range from handing them a product requirements document all the way to giving them RTL or completed layout. Your internal cost rise as the handoff gets closer to the chip, your contracting costs rise the more you hand over to the design house.
- Do it yourself. There are a few heroic industrial projects that have done this on a shoestring, but the principals were able to finance the development out-of-pocket, and were tremendously talented, experienced, and lucky. (And they knew how to make their own luck.) In general, resist the temptation to assume "you can do it cheaper" because if you haven't done it before, you can't.
Analog custom parts are outside my experience, but the cost in IP, tools, bodies, and FAB will still be significant. The tough part is that the custom silicon industry is built primarily to support digital designs, not analog. In particular, though "all digital circuits are really analog," over the past 50 years the industry has built lots of tools and practices that abstract the analog parts away for most of the digital design task. (Yes, I know about timing validation, signal integrity, electromigration, power net modeling, clock distribution, thermal modeling, and IO design rules -- I have
all those merit badges. Nonetheless, in modern synthesized designs, much of this is taken care of "under the covers" by CAD tools or design specialists. This is part of the de-skilling of the industry (sadly for those of us who know about TV, SI, EM, power...) and for the dramatic rise in productivity (good for everybody else).
I have worked with analog design houses, and they use many of the same tools as the digital folks, but have much more complex relationships with the foundry (or foundries) and often will push a test chip or two through the process before they are ready for prime time.
All that said, building custom or semi-custom chips is a hoot. (But it is a very expensive hoot.)