There are two time constamts. While charging during the short input pulse it is R12 times C3. While discharging it is R13 times C3. The pulse stretcher has a large dead time after each input pulse, since the output pulse is about 80 times longer. So after each 50 nsec input pulse it will take about 4 usec or more to measure the output pulse.
Regards, Dieter
Not sure where you're getting that from, R12 is part of a bias divider chain. Did you mean R9, annotated with the rather odd K12 rather than 0k12 or even 120R?
Anyway, for Zhou Quan's benefit, a quick explanation of how this works:
The divider chain formed by R10, R11 and R12 provides bias voltages of 3V to the base of VT4 and 1.7V to the base of VT5. VT5 in combination with the base bias and the 10k emitter resistor forms a constant current sink of about 100uA. VT3 and VT4 form a classic long-tailed differential pair, here being used as a current switch. The bias of 3V on VT4 sets the point at which this switched from one side to the other.
When the input, at R7 is low - VT3 is switched on, VT4 switched off and all the current from R9 is directed to earth via VT3. Meantime, VT5 acting as a current sink is discharging C3. The final voltage C3 settles to is difficult to be precise about without simulating it, but it's probably going to be about 1.2V to 1.3V.
Now, when a pulse happens the input goes high and VT3 switches off, VT4 switches on and R9 is going to act as a [rather poor] constant current source. The emitter of VT3 is going to rise to about 3.9V, so the voltage across R9 will be 1.1V and so it will source about 9.2mA. This 9.2mA will charge C3 via VT4 (All the time this is happening VT5 is still sinking ~100uA and slightly reducing the charging rate of C3). The voltage on C3 will rise roughly linearly at about 9.1V/us.
When the pulse stops the transistors will revert to their previous configuration. At this instant the voltage on C3 will be proportional to the pulse width plus its initial voltage. VT4 will stop providing charging current and the constant current sink formed by VT5 will now start to discharge the capacitor until it reaches its quiescent 1.2V to 1.3V. The time it takes to do so will be proportional to the input pulse width times the ratio of the net charging current (9.1mA) to the discharge current (0.1mA) or approximately 90 times longer than the input pulse.
Quan, try your simulation again with a 3.3V pulse. With the threshold being set at the base of VT4 being 3V you're probably just not raising the base of VT3 quite high enough to turn off VT3 reliably. Make your simulation time long enough to account for the pulse stretching.
Possible problems with this circuit:
It probably has poor linearity and temperature coefficient, I'd prefer to see the bias voltages set by diode wired transistors, and a proper transistor current source instead of R9.
There
may be a delay getting VT3 and VT4 out of saturation (if they get there), Schottky clamps between base and collector may help with this.
Certainly the linearity will be terrible for short pulses, better to feed it a pulse not between your asynchronous trigger and the next clock edge but the clock edge after that, adding a constant 1 clock time to the pulses fed to it to give it a decent sized minimum pulse to stretch.
The extremes of the compliance range of the pair VT4 and VT5 are only ~1.2V to ~3.5V (a range of 2.3V at most), which will limit the length of the maximum pulse you can feed into it (abs. max ~250ns) , and you will run into non-linearity before you hit the upper compliance limit, limiting the pulse length further (realistically perhaps 200ns) - this may or may not be a problem depending on your exact timings.
To deal with the drift that this is going to experience you'll need to calibrate it on the fly by feeding it a couple of pulses of known width (e.g. 1 clock time and 2 clock times) at regular intervals.
The thresholds that the capacitor voltage are going to be measured at are going to be highly dependent on what kind of input they are measured by. If you rely on a logic input as this current version of the circuit appears to expect that to add a
lot of drift. Ditto the load presented by the measurement input may be highly nonlinear and further dent the circuits linearity.
Edit: It's late, somebidy should probably check my numbers.