Si5351a questions

[Chris Wilson]

 Hi, bit of an oddball problem here (again.... ) I have a 1kW Class D low frequency 137 kHz LF ham band amp I built. It has worked fine for many months, after teething issues were eradicated thanks in no small  part to help from here. I like experimenting / learning /simplifying so when the designer of the QRP Labs U3S exciter I am using added some new firmware features I decided to try and take advantage of it. The U3S is based around a SiLabs Si5351a synthesiser chip. Originally I had the U3S send out a X2 frequency from CLK0 alone as the amp, a Class D dvice, halved it. (None of the circuitry after the CLK0 and CLK1 outputs in the U3S is used,  the Si chip *IS* the exciter with no amplification as shown on the U3S schematic from the BS170(s)).

 The new firmware allowed me to  delete one IC (the 74F74) and the 5V regulator and drive the FET driver IC at X1 frequency with the outputs from CLK0 and CLK1 of the Si5351a set to be 180 degrees out of phase. Before this firmware feature addition I used just CLK0 at X2 and the 74F74 IC did the division and its output drove an IR2110 FET driver IC. I swapped to an MCP1404 driver IC so I could delete the 5V regulator as well.

What is happening is with no voltage to the amp's FET drains the gate waveform is excellent. but as soon as even 5V is applied to the drains the gate waveform goes ragged and drain waveforms go HORRENDOULSY spiky. I also see seemingly random ultra short duration drop outs in the square waves from CLK0 and CLK1. These ultra brief glitches occur on CLK0 and CLK1 even when nothing is connected to them save my X10 scope probes. This suggests a firmware issue to me, but I may be missing something like impedance matching? This is also apparent whilst it is transmitting the digital mode WSPR from the U3S. Can anyone think of a reason for this please? It may be that the very infrequently used firmware option to have the Si5351a output on both CLK0 and CLK1 with a 180 degree phase shift is buggy, in which case I am solely at the mercy of the designer, but I want to be sure I am not missing anything before assuming this to be the case. So the changes from working perfectly to problematic are using a 180 degree phase shift from CLK0 and CLK1 adding two 82k resistors to the 12V rail to bias the input pins of the MCP1404, and using the MCP1404 instead of the IR2110 which needed a 5V supply as well as 12V.

If you are still with me, thank you!

[Chris Wilson]

Other images, (waveforms from scope capture).

[JohnPen]

Looking at QRP Labs write up on the Si5351A VFO it does refer to the Clk 0 and Clk 1 quadrature clocks only being used at frequencies above 3.2 Mhz.  The lower frequencies below 3.2 Mhz uses extra dividers in the chip which do not seem to be able to produce clean quadrature output clocks.  Hope this helps.

John

Edit:   There is also a comment elsewhere on the QRP site that if you wish to use frequencies below 3.2 Mhz  that you keep your original divide by 4 to produce the quadrature signal
for the low frequencies and then switch, using relays, to direct for frequencies above 3.2 Mhz.