I've also found it to be a good learning experience. Trying to figure out how to make my simulations more accurate has given be a very good feel for layout parasitics and such that I would have a hard time getting otherwise.
This is what I get from simulations, at least the SPICE ones. SPICE has been around for a long time, even when I was in school, but we barely used it much, I hated punching the cards, submitting the job through the operator, waiting for the results printout in the rack down the hall... etc... it was better and safer to develop instincts, and learn by doing, learn what works, what the tricks are, what to do, what not to do, where are the parasitics, etc. After a while you just know.
But these days having a SPICE simulator on my PC ( I use LTSPICE and TINA-TI because they are free ) is pretty damn cool
I am blown away that the design engineers can simulate the physical wafer process from the input files for some new chip, fed into Silvaco ATHENA, and it will simulate the process steps, trenching, oxidation, deposition, planarization, building the wells, the gate, polysi, halo and source drain implants, then it can extract the SPICE parameters from the simulation results of the virtual chip (!)... and can be used in a virtual circuit, if it fails, go back to some process parameters, tweak it and try again. They never have to actually make a die from the masks until they are really really sure.