Hope good spelling and punctuation are not high on their requirements!
Thankfully they are not, as I have accepted the position and soon will be an entry level ASIC developer.
In lieu of any notable ability for proper spelling or grammar, I would like to present a detailed analysis of the circuit previously described in exchange for aid rendered.
Grammarly was used to alter my thick southeastern American accent into something more palatable. And wolfram alpha helped solve the final R
4 equations.
This is the same circuit as before but drawn and labeled in a manner that may make it easier to describe in pleasant conversation. I will be focusing on the KCL/KVL derived equations, paying special attention to the details that explain the undesired behavior I witnessed when building this circuit on the breadboard. The overall functionality of the circuit is to convert an unknown resistance to a voltage in preparation for analysis using a fpga. I have the desire to include this design in my toolbox, ready to be configured and implemented at a moments notice. This requires a detailed understanding of the biasing resistors to guarantee stable and valid operation.
The unit under test in this example will be a PT1000 class B, with a maximum V
s=15v, and P
D=25mW or less to minimize self heating effects. Non-linearity of the unit under test is not a concern at the moment, merely obtaining the most accurate resistance measurement I can while quantifying error and noise to a known value. I wish to be able to study the effects of component tolerance on common mode noise rejection and output error. Before I can do any of that, I must first arrive at an ideal circuit that will meet specifications.
I have not completely error checked the math yet, so please point out any errors you find.Wheatstone Bridge Maths for Voltage Source
The values given are R
1,R
2,R
3,V
a, and V
wb$$V_{wb}=V_C-V_D \quad,\quad I_{R_1}=\frac{V_A}{R_1+R_2}\quad,\quad V_{R_1}=I_{R_1}R_1$$
$$I_{R_2}=I_{R_1}\quad,\quad V_{R_2}=I_{R_2}R_2 \quad,\quad V_C=V_{R_2}$$
$$V_{R_4}=V_C-V_{wb}\quad,\quad V_{R_3}=V_A-V_{R_4}$$
$$I_{R_3}=\frac{V_{R_3}}{R_3}\quad,\quad I_{R_4}=I_{R_3} \quad,\quad R_4=\frac{V_{R_4}}{I_{R_4}}$$
Combining all of the above terms gives the following solution to solve for R4
$$R_4=\frac{\frac{V_A}{R_1+R_2}R_2-V_{wb}}{(\frac{V_A-(\frac{V_A}{R_1+R_2}R_2-V_{wb})}{R_3})}$$
This method works, and is the logical pathway I used to solve for R4. But this circuit simply does not meet the requirements as specified.
Ultimately this line of logic is flawed due to the voltage drop equation being a unbalanced proportion. As the impedance of the two legs of the bridge grow further apart, the volts per ohm difference increases. With the bridges configured for the most accurate reading at zero0 C, the minimum difference of the difference ranges across 2.84x10
-5$$ V_{drop}=\frac{R}{R_{total}}*Vcc$$
After a lot of thought, I want to revert to my original though and use a current source to feed the bridge and create a more linear response based on
$$ V_{drop}=I*R$$
Wheatstone bridge with current source
$$I_{R_1,R_2} = \frac{R_3+R_4}{R_1+R_2+R_3+R_4} * I_t\quad,\quad I_{R_3,R_4} = \frac{R_1+R_2}{R_1+R_2+R_3+R_4} * I_t$$
$$ V_C=I_{r_2}R_2 \quad,\quad V_D=I_{R_4}R_4 $$
$$ R_4 = \frac{R_2(R_3I_t-V_{wb})-V_{wb}(R_1+R_3)}{R_1I_t+V_{wb}} $$
Using a spreadsheet to generate charts which compare the two wheatstone bridge's V
wb. the results are very promising.
With the bridges configured for the most accurate reading at zero0 C, the minimum difference of the difference ranges across 7.67x10
-6that looks like a 369.75% increase in linearity.
Factoring in that I am not a math expert, I would like to request a second opinion on these figures.
(ok. take a break from the ai speak, I typed in "I dont know what im doing here, What yall think about that", that^^^ is what was spat out. AI has its uses)
First is the difference between V
wb per change in the PT1000 across its entire valid range of -50c~550c or 807.5~2925ohms
And the last is the difference, in the difference between V
wb per ohm of change. This chart directly shows the non-linear errors
By using a constant current source to feed the wheatstone bridge, the linear operation has increased by an order of magnitude, bringing the non-linear error to less than that generated by component tolerance.
Non-ideal effects which have prevented proper operation of the circuit include
V
C or V
D falling below or above the Output Voltage limits of my device at current Vcc (LM324A @ +5v )
The same can occur across resistor R
5 per the following formula, in which the input buffers are not able to apply the needed voltages to balance the inverting and non-inverting inputs due to ether the gain of the input stage or the output voltage limits.
$$V_{wb} * (1+\frac{2R_6}{R_5}) >= Vcc *\frac{R_5}{2R_6}$$
ToDo:
Model noise sources,
Component tolerances error calculations
Low pass filters
the next 500 pages of
Op amps for Everyone