I'm trying to solve a problem from AoE 2nd edition. I don't have access to solutions. If someone has a link to a solution manual, that would also be awesome.
The question is pretty open-ended. It just asks to describe how the circuit works (with regards to input bias current cancellation).
This is my explanation, can anyone confirm or add to it?
- This is a differential amplifier, with high gain (R1/2re, where re is determined by collector current with the relationship Ic*VT, where VT is ~25.3mV at ambient temperature).
- Q3 and Q4 form a current mirror, keeping their collector (and emitter) currents the same.
- The curent source makes the CMRR very high (since current sources have near-infinite output impedance).
- the current source pulls an equal amount through Q1 (and Q2) and the corresponding transistors on the other side
- Since collector current of Q1 and Q2 are approximately the same, and they're beta matched, they will also have the same base current.
- But since Q3 provides all of Q2's base current, Q4 will need to provide that same current to Q1's base. So all the DC biasing for the differential amplifier comes from the "VE + 2V supply"
- input impedance is high (Q4's collector looks like a current source with negligeable admittance, Q1's input impedance is 2re*(beta+1))
- VE+2V rail is used because we want it to be as low as possible. If we used Vcc, Q2's emitter would sit at two diode drops under Vcc, which would severely limit our output swing.