Daisy Chainable Clock Modules?

[sidereal]

Hi

The purpose of this post is to learn about clock modules in various ways, so please bare with me.

Are their Clock IC-s. where you can connect them with one another, so that they could 'synchronize' themselves and improve the regularity? I know that you can take colpitt's oscillators and feed them with a reference signal, and the oscillator will "latch" onto it. This is called "Injection locking". I also know that it is possible to do that with 2 colpitts, where the output of one is used as a reference of another.

But are their some ready to use clock modules, where you can do exactly this, take the output of one, and feed a branch of it, may be via an amplifier to the reference of another, and keep on daisy chaining them one after one? Thank you.

[Terry Bites]

I'm not sure what you mean by "clock modules". RTCs? synth sequencer? Show us a picture.
Yes, there are plenty clock distribution ics aka fan out buffers.
They would be used a the system level not interconnected systems.

You wouldn't daisy chain them becasue of the internal delay will cause them to lose sync.
If you needed many instances of the same clock, the solution would be to drive many clock distributors from a single clock source.

If you need to lock one oscillator to another, maybe at the same or even a different frequency, then a PLL is the thing.
With a simple PLL you can generate integer multiples of the input frequency.
wikipedia.org/wiki/Phase-locked_loop

You will find very specialist (and very expensive) "network clock synchroniser" ics. I that you're after?

What is it you are trying to do.
Why?

[CaptDon]

A master reference one-pulse-per-second can be used to discipline all kinds of clocks although you may have to build the integration. Typically the slave clocks run ever so slightly slow and the master pulse will push the 1 second rollover counter I.C. The are also 'dummy' slave clocks with no internal clocking. They are simply serial in / parallel out shift registers which receive a serial data string from a master clock and then display the data.

[sidereal]

My idea is to reduce errors.

Any clock will have some errors. say, at any given moment, one clock is beating with f + df1 and the other with f + df2, wherein the target is f. I am hoping somehow to combine these clocks with each other, so that the final result is f + df3 such that df3 < df1 and df3 < df2. I know this can be done wiht colpitts oscillator at least in theory, I want to learn about practical implementations. Thank you.

[Terry Bites]

So you want to take the average of two frequencies clocks to produce a third frequency.

If you put the two clocks into an XNOR gate and pass the result through a low pass filter you get a voltage proportional to the frequency difference.
This error voltage might be used to control a varactor or VCXO.

[sidereal]

Hi Yes, that I a nice idea. I will test it out.