First High Speed Circuit FPGA LVCMOS or LVTTL

[simontheu]

Hi All,

Love the blog and the forum, its a great community, also love 'The Amp Hour'.

Im trying to interface a GS9032 serialiser chip for video. It takes in what it quotes as CMOS/TTL 10 bits in parallel plus a video clock. The clock is running at 27Mhz. (This being the parallel rate, to end up with 270Mbs serial rate.)

After faffing for some time with bypass capacitors and power supply. I have finally got it so that the chips internal PLL is locked. But Im struggling to get any usable data. I've never driven data this fast and Im only sending it down jumper wires between my circuit and the De0 Nano FPGA Board. Ive only got a 100Mhz bandwidth scope so everything looks fairly sinusoidal, but ok.

My question is whether I need any termination resistors if I am driving this chip from an FPGA? (Cyclone IV on De0 Nano)
And what interface type out should i use. 3.3V CMOS 3.3V TTL?

Here is the circuit I have made, its from the GS9032 data sheet. Available here:http://downloads.semtech.com/extranet/document/9548


https://www.dropbox.com/s/5ufjwvx1gouf1tz/circuit.png?n=278467836

Any help greatly appreciated.

[free_electron]

Wires ? You are nuts .... This needs a board.

[simontheu]

The jumper wires are between the boards. I have made a board for the serialiser section.

[Alexei.Polkhanov]

LTTTL (3.3V) and LVCMOS (also 3.3) are slightly different in levels. (see 2 most right columns on diagram here: http://www.interfacebus.com/voltage_LV_threshold.html). 27 MHz LVCMOS signal should not look sinusoidal on 100MHz scope.

What do you mean by termination resistors? Resistors for series termination?

To have meaningful discussion about termination and signal integrity problems you need to capture signal on oscilloscope and post pictures here.
There are plenty of configuration parameters that you can apply to Cyclone's I/O ports in Pin Planning in Quartus II. Nice to see screen capture of that as well.

Make sure it is all correct, then if it still not working - look at the signal on oscilloscope - you may want to explore different termination options (22-27ohm series resistors may help if you have lots of overshoots/ringing) or if tracks are too long (> 4-7 cm) you may want to add bus transceivers. With transceivers you can make it work with long (20-40 cm) wires.

[T3sl4co1l]

Pics or it didn't happen. 

Layout, setup, scope traces... even how you're probing it.

[hamster_nz]

As pointed out, 27MHz is hard to do with wire jumper, however it is possible. I've interfaced a camera module at 25MHz with reasonable results. The shorter the cables the better.

Is your FPGA design respecting setup and hold times? 

More specifically, in simulation (and/or on the scope) are the edge of the PLCK signal NOT align with the edges in the data signal?

Is your FPGA design running at 27MHz or 54MHz?

If you are running at 27MHz, are you using good clock forwarding techniques (e.g. driving a DDR register), or just presenting a clock signal to the outside world?

[jahonen]

Problem might be due to insufficient ground connection between your FPGA and serializer. This is quite often overlooked.

If you are using longish wires to connect the FPGA and serializer, you'll absolutely need individual ground wire for each signal, especially clock, connected to ground plane at each end (not in same single ground pin on a pinheader!). These individual ground wires should be packed as close as possible to each data/clock line to have desired effect.

Also, it might be possible that clock has too much crosstalk to data signals, changing the data just on the active edge.

Having a series resistor at the driving end is a good idea if drive strength can't be lowered to suitable value on the FPGA. Suitable value is usually a quite bit higher when using this kind of connection (this kind of connection has quite high characteristic impedance), you might try something like 75-100 ohms or so.

Regards,
Janne

[Scrts]

This chip does SMPTE-259M right? So it's Serial Digital Interface (SDI)?
Why do you need that chip at all??? There's Altera IP core for like 10+ years for that and it gives LVDS output of 270Mbps for SD-SDI there. The same for DVB-ASI. You only need genlock for reception, not transmission.

[simontheu]

27 MHz LVCMOS signal should not look sinusoidal on 100MHz scope.

What do you mean by termination resistors? Resistors for series termination?

When I say sinusoidal I mean not exactly square. Its not a pure sine wave.

And as for termination resistors, I am asking whether they should exist, be series or parallel, and what value.

To have meaningful discussion about termination and signal integrity problems you need to capture signal on oscilloscope and post pictures here.
There are plenty of configuration parameters that you can apply to Cyclone's I/O ports in Pin Planning in Quartus II. Nice to see screen capture of that as well.

Make sure it is all correct, then if it still not working - look at the signal on oscilloscope - you may want to explore different termination options (22-27ohm series resistors may help if you have lots of overshoots/ringing) or if tracks are too long (> 4-7 cm) you may want to add bus transceivers. With transceivers you can make it work with long (20-40 cm) wires.

What do you mean by bus transceivers? The tracks are short on the serialiser side and the FPGA side, with about 10cm of jumper wire in between.

Im also out of town at the minute, but should be able to supply the pictures to help on monday.

Thanks

[simontheu]

This chip does SMPTE-259M right? So it's Serial Digital Interface (SDI)?
Why do you need that chip at all??? There's Altera IP core for like 10+ years for that and it gives LVDS output of 270Mbps for SD-SDI there. The same for DVB-ASI. You only need genlock for reception, not transmission.

Yes its SDI, and I want to upgrade to HDSDI when i can get my head around this, (74.25MHz )

I can't run the IP core on a cyclone IV. Plus I have to pay for it and I can't poke around in its inner workings.

Thanks everyone for your replys, I will post some more pics of my data and clock traces and start to try my luck with some resistors and more ground wires.

[simontheu]

The attached pictures will hopefully point out my issues. The clock signal is a dedicated clock line from the PLL.

[simontheu]

Continued... The signal line doesn't really look like anything, is it cross talk?

[free_electron]

that thin trace going around the board better not be the power supply for that chip.....

also the interconnect with loose wires is not good.

[T3sl4co1l]

What scale are those scope shots?

What does the cable look like?  Pinout, assignments, length, impedance matching...?

Tim

[Alexei.Polkhanov]

That clock signal - you say it is coming from PLL. Do you mean from PLL inside FPGA? It (signal) looks OK. At what location did you probe it? At GS9032 clock input pin (PIN 11 on GS9032)?

Data signal (you have rotated 90 on your photo  ) looks as if it is getting messed up due to reflections. How does it look like if you disconnect the cable from that pin and connect it to ground through 50-75ohm resistor?

If I understand right Cyclone FPGA that you are interfacing can accept 3.3V input, but it can only send 3.0V out. Try series terminating resistor (place 27ohm resistor in series) and check what happens. You can change drive current to 8ma in Quartus instead of default 2ma?

I had 10cm ribbon cable connection working at similar speeds - my clock was 60MHz, but eventuall I had to buffer everything with transceiver. Kind of like on schematics in this datasheet: http://www.analog.com/static/imported-files/data_sheets/AD9283.pdf

I found few pics online that show how to better interface extension board(s) to Nano as well.

[simontheu]

that thin trace going around the board better not be the power supply for that chip.....

also the interconnect with loose wires is not good.

Do I need thicker traces (much) for power supply or use a copper pour?

Ill work on the interconnect.

[simontheu]

That clock signal - you say it is coming from PLL. Do you mean from PLL inside FPGA? It (signal) looks OK. At what location did you probe it? At GS9032 clock input pin (PIN 11 on GS9032)?

Data signal (you have rotated 90 on your photo  ) looks as if it is getting messed up due to reflections. How does it look like if you disconnect the cable from that pin and connect it to ground through 50-75ohm resistor?

If I understand right Cyclone FPGA that you are interfacing can accept 3.3V input, but it can only send 3.0V out. Try series terminating resistor (place 27ohm resistor in series) and check what happens. You can change drive current to 8ma in Quartus instead of default 2ma?

I had 10cm ribbon cable connection working at similar speeds - my clock was 60MHz, but eventuall I had to buffer everything with transceiver. Kind of like on schematics in this datasheet: http://www.analog.com/static/imported-files/data_sheets/AD9283.pdf

I found few pics online that show how to better interface extension board(s) to Nano as well.

Solid gold Alexei thank you.

The PLL is in the cyclone FPGA. I probed it near the GS9032.

Will try the suggestions for the data line and get back here with the pics. Can I be cheeky ask where the values for termination come from? Both the 27ohm and 50-75ohm?

[Alexei.Polkhanov]

Will try the suggestions for the data line and get back here with the pics. Can I be cheeky ask where the values for termination come from? Both the 27ohm and 50-75ohm?

50 ohm is standard matching impedance that most interfaces designed for, 75 ohm often used in telecom equipment instead of 50.
I took 27 ohm just from my memory - that kind of resistance I used for series termination in similar situation.

In order to get correct value for your final design on PCB you may want to simulate it. Higher the speeds more important signal integrity is. Look at this paper from Altera http://www.altera.com/literature/hb/qts/qts_qii53020.pdf. (page 6-15 looks interesting) They have an example of simulation in HyperLynx. HyperLynx mentioned most often with respect to signal integrity simulation.  Altium Designer has some abilities built in. Problem of course is that hard to get accurate model for a jumper wire. If you look at any signal integrity book or paper - they usually have lots of examples with signal captured. You look at your case and find similar picture - this is how you find out what problem could be - is it an overshoot, reflection, capacitive input/low drive current etc. then try to apply same mitigations experimentally. At least this is my ad-hoc method of dealing with it when prototyping.

Otherwise there are books like http://www.amazon.ca/Signal-Power-Integrity-Simplified-Edition/dp/0132349795 - Signal and Power Integrity Simplified ... simplified on all  792 pages 


 

[miguelvp]

The DE0-Nano has a 50MHz reference crystal, the speed rating is a 6 so it can switch at 400MHz (I think) rating 8 being 333MHz (BeMicro for example)

I was able to drive my Nano at 330MHz:


But note that the 3 channel video DAC had no problem at 162.0 MHz to drive a 1600x1200@60Hz display.



As for termination the DAC board I used it's 75 Ohm terminated since VGA monitors have a 75 Ohm resistor. But I guess I'm not understanding what you are driving, the datasheet you linked has the sample circuit output using 75 Ohm resistors.

Also the output voltage I used was 3.3 V LVTLL driving an ADV7125.

https://www.eevblog.com/forum/microcontrollers/ov5640-hack/msg447100/#msg447100

[Alexei.Polkhanov]

The DE0-Nano has a 50MHz reference crystal, the speed rating is a 6 so it can switch at 400MHz (I think) rating 8 being 333MHz (BeMicro for example)

Speed of reference crystal does not really matter since you can set any multiplier on PLL.

Theoretical speed of 333 MHz does not not really define at which speed your design can run specifically - it all depends on hold time/setup time, latching or in other words it depends on how good your Verilog code is. Many of complex cores run at most 90 to 160MHz while clock can go as high as 385 MHz and there are many reasons for that.

Quartus usually tells you at what speed you can run your design without violating anything.

[miguelvp]

The Altera FPGAs have a speed grade for the theoretical maximum.

The DE0 Nano's Cyclone IV is rated at a speed grade of 6, the maximum I tried to push it at was 333MHz I think the theoretical maximum is 400MHz to meet setup/hold times, but never tried to push it that much.

Yes, the PLL allows you to set any multiplier divider combination to get to your needed target clock, or close to it.
For example if I wanted a 193.16 MHz clock to drive a monitor at 1920x1200@60Hz, I will have to multipy by 4829 and divide by 1250, not sure if the PLL will let me use numbers that high (I'll try later).

Reason I selected 162.0 MHz was because of the Vesa standard at that resolution @ 60 Hz.

http://tinyvga.com/vga-timing/1600x1200@60Hz

I mentioned the maximum frequency because of the BeMicro documentation on accessing the DDR3 memory, it mentions the speed will be determined by the speed grade and gives the following table:

Code: [Select]

Temperature and       Maximum Frequency
Speed Grade              of Controller (MHz)
C6                              400
C7                              333
C8                              333
I7                               400

The OP's code is video output as well so he should be fine if he only needs 27 MHz. Set the PLL to multiply by 27 and divide by 50.

But yeah timing analysis is a pain. Thank God Quartus has good tools.

[hamster_nz]

Yes, the PLL allows you to set any multiplier divider combination to get to your needed target clock, or close to it.

There are some limits... the PLL needs a VCO freq between 600MHz and 1300MHz,  The output freq is Fout =  Fin * M/(N × post-scale), where M is between 2 and 32, and N is between 1 and 32, and post-scale is between 1 and 32.

Most display devices are pretty flexible - I drive 720p at a nice even 75MHz, rather than at the standard 74.25MHz, without any issues, but it is better to drive 640x480 at 25MHz than 24MHz, as most TVs will reject the slow bit clock as being out of range.

The time I do have pain is when driving I2S clocks. Trying to hit frequencies like 12.288MHz is awkward. I have soemtimes resorted to stupid things like a 32MHz clock / 25 * 48 = 61.440MHz, then output a bit every 5 cycles (using a DDR register to make the high/low time of the clock signal to 2.5 cycles). Yuck!

[simontheu]

First of all. Sorry. I messed up my parallel output pins. It was one of those things where I always thought I would of done that first. Anyway, I have serialised data!!! Whoopeee. Although I haven't got a device to lock to it yet, but I think i need to overhaul my VHDL.

Ive attached some of my signal lines that were probed close to the serialiser with a 100Mhz 10x probe on my beautiful Tek465. The scale was 2v per div.

Before I respin the board, should I play with termination resistors?

[T3sl4co1l]

Eye diagram is okay, but the bounce definitely leaves something to be desired...

Pics of layout..??

Tim

[simontheu]

TODO:

1. Increase track width of positive power rail.

2. Include 25 Ohm series termination on signal lines.

3. Change electrolytic to surface mount capacitor.