is it fine to have floating pin with NE555 set for VCO

[LaserTazerPhaser]

Would the floating discharge terminal cause damage to this oscillator?

[T3sl4co1l]

No, it's an open collector.

Tim

[T3sl4co1l]

It can be completely open.

[StillTrying]

Is 15nf between discharge to gnd fine?

It could be directly shorted to GND on your schem, (but not V+) with no effect, because discharging any cap to GND is what DIS does.

[magic]

You may also connect it to VCC with no effect if you put an LED and series resistor in between

Or leave it floating because it really doesn't matter

[Zero999]

Would the floating discharge terminal cause damage to this oscillator?

Pin 7 just goes to a transistor's collector. There's no way it can be damaged by not connecting it to anything, just don't connect it to a voltage source, without a suitable current limiting resistor.

Note the circuit you've posted won't work quite so well in real life, compared to the simulator program. This is because the SPICE model doesn't accurately simulate the 555's output stage. The simulator shows the output swinging between the negative and positive rails, which will not happen if you built this circuit on a breadboard. In reality, the 555's output stage is not a perfect switch, but two bipolar transistors. The upper transistors are a Darlington pair, configured as a follower and will drop at least 1.2V and the lower one is in common emitter configuration and will pull the output close to 0V.

Refer to the following parts of the datasheet.
Figure 2, page 2: the internal schematic, note the transistor on pin 7 (Q14) and the output stage (Q21 & Q22 on the high side and Q24 on the low side).
Figures 6 to 8, page 6: some graphs showing the low output voltage drop vs current. Note it's near zero, at 1mA.
Figure 9, page 8: a graph showing the high voltage drop vs current. Note at 25^oC it's fairly close to 1.4V, irrespective of the current and  very temperature dependant.
https://www.st.com/content/ccc/resource/technical/document/datasheet/ba/0a/d7/6e/7c/db/4e/12/CD00000479.pdf/files/CD00000479.pdf/jcr:content/translations/en.CD00000479.pdf

If you built this circuit, the output will swing between about 7.8V and near 0V. The duty cycle will not be 50%, because the capacitor will take a little longer to charge, than discharge. It will also be quite sensitive to changes in temperature, as the voltage drop of the Darlington part has a negative temperature coefficient. Exercise for the reader to figure out whether the duty cycle will be above, or below 50%.

[MarkF]

It seems to me that the Pulse-Position Modulation application in the datasheet is what you are looking for. 
If you want a 50% duty cycle you would need a 2nd stage to divide the NE555 output.

[LaserTazerPhaser]

It seems to me that the Pulse-Position Modulation application in the datasheet is what you are looking for. 
If you want a 50% duty cycle you would need a 2nd stage to divide the NE555 output.

(Attachment Link)

An ne556 is ideal for this.

[Gary350z]

Would the floating discharge terminal cause damage to this oscillator?

Interesting question.
At first you would think the open collector would be ok, but when the discharge transistor is off and the collector is floating, a static discharge could excede the transistors max collector voltage and damage the IC. The above mentioned datatsheet says the absolute maximum ESD is from 100 to 1500 volts. So it looks like a static discharge could damage the IC when the discharge transistor is off.

[T3sl4co1l]

ESD of hazardous magnitude will damage it, regardless whether the transistor is on or off, or wired or not...

Tim

[StillTrying]

An ne556 is ideal for this.

I've made a few attempts to completely separate the frequency and duty using a fast CMOS TC556. They weren't very good for the 1Hz to 2MHz range I was aiming for, but OK for frequency ranges up to about 100X. At mid frequencies 1% to 99% duty was possible, at MHz you're stuck with 40%-60% of adjustment.

https://www.eevblog.com/forum/projects/change-pulse-width-of-a-signal/msg1129000/#msg1129000

[Gary350z]

ESD of hazardous magnitude will damage it, regardless whether the transistor is on or off, or wired or not...

Tim

Question for Tim,
If you have a discrete small signal bipolar transistor wired up with full base drive, and an open collector, do you think a static discharge on the collector will destroy the transistor? I'm talking about an everyday static discharge, not like a 10 inch spark.

PS. I noticed your website at the bottom of your message, I'll have a look.

[T3sl4co1l]

Diodes Inc. for example rates their MMBT3904 for 4kV HBM ESD.
https://www.diodes.com/assets/Datasheets/ds30036.pdf

Doesn't matter which combination of terminals, as far as I know.

Tim

[Ian.M]

All BJT junctions will Zener or Avalanche under sufficient reverse voltage stress.  Whether or not its destructive depends on a number of factors including pulse energy, how vulnerable the silicon structure is to hot-spotting, and if the peak emitter current is sufficient to fuse the bond-wire (as the collector is usually directly bonded to the tab or leadframe).

Its possible to get a rough idea of the currents and energies involved by SPICE modelling.   I've attached a LTspice sim of a HBM discharge to the collector of a 2N3904.   If you are interested in the reverse breakdown of the B-E and C-B junctions, the LTspice 2N3904 model has to be patched with realistic Vceo and reverse Vbe breakdown voltages as the standard.bjt library model doesn't specify them so defaults them to infinity.

N.B. Results are only as good as the transistor model used.  As most published transistor models don't specify breakdown behaviour, simmed peak currents and pulse energies should be viewed with scepticism. I usually use this sim jig for evaluating theoretical designs of ESD protection networks to quickly eliminate obviously inadequate designs.  Real world testing is still essential.

[Gyro]

Instead of agonizing about it too much, wouldn't be easier just to decouple the discharge pin to ground with a cheap 100nF Y5U ceramic. That would be enough to absorb any reasonable ESD spike and leaky enough to prevent long term voltage buildup.

[Ian.M]

Why would you even need to do that?  Its open collector (or open drain for a CMOS 555) so you can simply tie it to ground.   

If you need to bring Discharge out as an external connection from your complete circuit, a 50mA polyfuse in series and a suitable voltage rating unidirectional TVS diode shunting it to ground would probably be the best option for ESD and over-current protection with minimum interference with its normal  function.

[Gyro]

Sorry, I didn't notice that the discussion had moved on from the 555 discharge pin to something more generic. Yes, of course grounding it would be simpler (in fact suggested earlier in the tread).

[T3sl4co1l]

Not to forget that, if your core circuitry is subject to ESD, you've already failed in some spectacular and embarrassing way.

Tim

[Zero999]

Yes, of course it can be damaged by ESD, if left open, but it's quite unlikely, unless it's connected to a long PCB trace. If it makes the PCB layout more difficult, then I wouldn't bother grounding it, otherwise if it makes no difference to the PCB, ground it.