bus slice duplicate errors

[vixo]

Hi, I've made a multisheet design in altium, but on compiling I get some errors - Duplicate Bus Names Bus Slice. My design has a top sheet(sheet1), which contains four subsidiary sheets(sheet2), and each of those four sheets contain sixteen copies of a third sheet(sheet3) - hope that's clear.

The error seems to be occurring because the four sheet2s have a bus inside them, and when that bus is duplicated it isn't automatically renamed something which distinguishes it from the other sheet2s - Im guessing this because I get the error three times, so the first instance the bus is named and the further three times the sheet is duplicated creates errors. If i increase the number repeats to 5, i then get four errors. These are the only errors I get, so all the nets and components have been renamed ok.

The top sheet also contains a net and this causes no problems, so I suppose the naming of the nets works ok. The project net identifier scope is set to automatic, and seems to have defaulted to hierchical as this option give the same errors.

anyone have any idea why this is happening?   

[T3sl4co1l]

Might need strict hierarchical definition?  Beware your supply nets.

I've not needed buses within repeated channels, myself, so I don't know this specific case.

Tim

[vixo]

unfortunately doesn't seem to be that simple - i still get the same errors with hierarchical selected!

[ajb]

Are you using the buses to bring signals in and out of the sheets?  If not, you may be able to use individual net labels to make the connections between bus members, and leave the bus as a graphical element only.

[vixo]

yes, im using them to supply each of 16 signals to each of the repeats of sheet3 - see the image attached . the buses causing the problems are led_gnd[16..1] and selectx[16..1]

[T3sl4co1l]

Does the reverse order matter?  I always thought it was [1..16].  Why it should be different from VHDL notation (higher-lower) or if it matters, I don't know..

[vixo]

nope, still no cigar  I tried that already

I think you can use either forward or reverse order and will reverse which number net goes to which number repeat

[ajb]

Can you tell what names the nets in each sheet are winding up with?  The error you're getting sort of sounds like the bus names are duplicated by net names, does Altium add a suffix to the bus name on compilation like it does with nets in a multi sheet design?  I've only used nets twice in Altium, and only in a top level sheet...