Easy way to generate matched length traces?

[8086]

Got some DDR SDRAM attached to an ARM device. Is there a way to generate the "squiggly" matched length traces for better signal integrity? Is it even going to make a difference at 133MHz?

[free_electron]

Set up a net class, throw the nets you want to equalise in there. Setup design rule to feed it the max tolerance and then kick in the matched length tuning

[AlfBaz]

Is it even going to make a difference at 133MHz?

Down load all the info on the arm you are using, you should find info on routing rules for the DDR bus. It generally will tell you how close to keep the lengths and may have special requirements or length constraints for clock signals
EDIT: one particular arm I used had an errata that required DQS lines to be between 2" to 4" longer than data lines as a work-around

[8086]

Thanks guys, I'll give it a go.

[marshallh]

No need to worry much with DDR266 (133mhz clock). Is this a 4layer design? Then stick to the top/bottom for routing. Only dip into the power layer in case of emergency. Don't slice up your ground plane.
If you still want to length match for practice, move around your routes so that they are spaced further apart. Look through your Net View and see what your longest DDR net is.

Project Options > Allow ports to name nets, Update PCB from schematic

Interactive Length tuning > Tab > Enter in your longest net length.
Press F1 while in the tool to see hotkeys that affect meander parameters.
The tool is kinda dumb, it will only meander across contiguous routes. Use Transparent view to see where you have discontinuities. Play around with the start/stop locations (turn off object snap) to see how it affects the meander generation.


Here is a baby x8 I just did. Command/addr are routed on bottom and data on top. Diff clock terminates through R5. Cap on bottom is for Vref. Treat DQS like a clock.

[jamiechi]

I just found this. It is a more comprehensive document on high speed design in Altium.  http://fplreflib.findlay.co.uk/articles/37941%5CHiSpeedDesignTutorialforAltiumDesigner_long.pdf

[sacherjj]

Keep in mind that speed of signal on surface layers is different than speed of signal in buried layers.  I'm getting into the high speed stuff myself and Ott's book on "Electromagnetic Compatibility Engineering" was worth the price for many chapters by themselves.  The PCB stackup chapter is great for thinking through this stuff.

Robert also has some good Altium vids on DDR routing.  https://www.youtube.com/user/matarofe?feature=watch