No need to worry much with DDR266 (133mhz clock). Is this a 4layer design? Then stick to the top/bottom for routing. Only dip into the power layer in case of emergency. Don't slice up your ground plane.
If you still want to length match for practice, move around your routes so that they are spaced further apart. Look through your Net View and see what your longest DDR net is.
Project Options > Allow ports to name nets, Update PCB from schematic
Interactive Length tuning > Tab > Enter in your longest net length.
Press F1 while in the tool to see hotkeys that affect meander parameters.
The tool is kinda dumb, it will only meander across contiguous routes. Use Transparent view to see where you have discontinuities. Play around with the start/stop locations (turn off object snap) to see how it affects the meander generation.
Here is a baby x8 I just did. Command/addr are routed on bottom and data on top. Diff clock terminates through R5. Cap on bottom is for Vref. Treat DQS like a clock.
![](http://img820.imageshack.us/img820/2808/6y1d.png)