How to do a net tie between two copper pours?

[mrflibble]

I have two ground planes, DGND and AGND that I'd like to connect at 1 single point. I'm currently trying to use a net tie for that, but as you can see in the attached screenshot that's not working too well.

I have "Pour Over All Same Net Objects" selected for both polygon pours, and "Connect to Net" to AGND and DGND respectively.

The net tie is a track with a pad at each end, and Component Type is set to Net Tie.

I thought that should work but obviously not. What am I missing here?

Edit: Incidentally, yes I did do a "Repour All".

[Skimask]

Add a component like a resistor and set it's value to 0 ohms.

[mrflibble]

Besides that one. Should have mentioned that I didn't want to use that option. I want a straight track connecting the two planes, not a 0 Ohm jumper resistor. Hence the net tie.

[Skimask]

(Assuming you're using EAGLE...)

How about changing those 2 nets to a different class with "0" clearance.  Later when doing the DRC, "Approve" those errors if needed...

[mrflibble]

Using Altium. And I'm trying to do this without having to ignore DRCs. I already know a workaround that involves ignoring DRCs.

To wit:
- remove net tie
- repour polygons
- THEN place the net tie
- ignore the inevitable DRC violations
- done

But I'd like something a bit nicer than that.

[gxti]

I could never get net ties to work, pretty sure they don't do anything at all. What you can do is create a new DRC rule under "Short Circuit", pick your first net as the first condition, second net as the second condition, and check the box to allow short circuit. Then draw a track from one to the other and make sure it is set to one of the nets. The most common mistake I keep making is ending up with an object with no net at all because Altium gets confused.

I'm not entirely sure it will actually pour over the track but you can get creative. For example place a via in the middle and draw a track to each side with that side's net, or make a 0 ohm resistor in your schematic, set type to "Standard (No BOM)", and draw the shorting track on top of the component.

[Rufus]

The net tie is a track with a pad at each end, and Component Type is set to Net Tie.

I thought that should work but obviously not. What am I missing here?

The pads of a net tie have nets as connected in the schematic. Other primitives default to no net although if not locked you can edit and change the net. The track between your pads in the net tie has no net which prevents the polygons pouring over it and because it ends in the middle of the pads prevents polygon connect tracks being placed on the pads.

You could change the net tie footprint to consist of just two thin rectangular pads which overlap in the middle. Alternatively you could split the connecting track in the middle and manually assign the desired net to each half.

If you only use pads to make the net tie you have control over which parts of the shape get assigned which net.

[free_electron]

Ah that problem.

make a pcb footprint consisting of 2 pads. call them 1 and 2.

Between the pads draw a piece of line or a fill. DO NOT CONNECT FROM CENTER TO CENTER ! <-this is the cause of the failure.


make a schematic symbol with 2 pins. set type to NET TIE or NET TIE (in BOM)

try it now. it will work perfectly.

if you touch the center of the pads with the line or fill the router can't connect as the clearance drc doesnt let him go there. ( the fill or track has no net. and the rules prefent him from shorting this. only the 'net tie' argument suppresses the short violation. it does not block the actual router...

[codeboy2k]

I always use a 0-ohm resistor (or 2 in parallel)  to tie analog ground to digital ground. This has no issues with needing to mess with net ties, or approving DRC errors. 

It adds little to the BOM cost and makes it easy to separate AGND from DGND for performance tuning or diagnostics on the bench during prototyping. If I have something weird or unexpected happening, then I can quickly separate AGND from DGND and power the analog portion from a bench supply to test these two halves separately.

Also, they give me more choice.  For example, if I am not sure where is the best place to tie AGND to DGND, then I will often put the location of the tie-point in more than 1 place on the PCB, at least on the prototype: (A) at the power entry point (B) at the ADC, (C) some other place that might seem right.  Then I can test each grounding point as to how it affects performance.  Depending on the design, I might use between 1 and 4 0-ohm resistors as a link.

The 0-ohm links allows you to measure separate analog and digital currents (again, useful for prototype stages).  You can put a differential probe at that 0-ohm point to see what's going on between your grounds.  I often use 0-ohm links coming off all my regulators to the power nets too, since I can use them to measure currents.

Finally, a 0-ohm tie point gives the option of upgrading to a ferrite bead if you find it's needed.

[gxti]

Thanks for that, last time I attempted to use net ties there was no documentation. Just a glossary-style "This is a net tie. It ties nets." with no explanation of how to use it. The DRC method also works well and you can use it to "pre-set" solder jumpers without having DRC errors.

[poorchava]

Make a special component which has 2 smd pads on top layer connected by a slab of copper on top layer. Will definitely work but the copper slab amy cause DRC violation here and there (or you can add a DRC exception to ignore short-circuit violation for that component)

[mrflibble]

Thanks for all the replies, those were useful! Of course not 100% in the way I would have liked it, because that would have been too easy.

@free_electron: I tried your suggestion, but it didn't help in getting the polygon pours to connect as intended. Your trick of almost but not quite connecting the pads to the track does look useful however, so I will try that one again when I have a bit more time.

In the end I used gxti's method of placing a track, assigning it a net (AGND) and then setting up a DRC that allowed a short-circuit between AGND and DGND. For now this is the option that is the least amount of hassle.

I will for the next PCB however try all the suggestions again to see if I missed anything.

[Rufus]

In the end I used gxti's method of placing a track, assigning it a net (AGND) and then setting up a DRC that allowed a short-circuit between AGND and DGND.

Which will also allow shorts between those nets anywhere else.

If you had made a net tie footprint from two pads as I suggested polygons would pour as shown in the attachments with and without a direct polygon connect style rule for those pads. The polygons are displayed in draft mode.

[AlfBaz]

Which will also allow shorts between those nets anywhere else.

A possible work around for this ( a little more work) is to create an intermediary net (eg GNDTIE) and create 2 rules allowing a short between gnd and gndtie and agnd and gndtie

[mrflibble]

If you had made a net tie footprint from two pads as I suggested polygons would pour as shown in the attachments with and without a direct polygon connect style rule for those pads. The polygons are displayed in draft mode.

Well, I used the other method because I couldn't get it to work the way I wanted to in the time allotted. And I wanted to finish the PCB, so I picked the method that gave me the desired copper shape. Your first screenshot is almost what I want, but not quit. I don't like the way the copper pulls back.

In any event, today I did figure out how to get it to do what I want. And it is indeed your 2 overlapping pads. But then with the addition of putting the net tie component in a component class, and adding two rules. One rule for polygon connect style, which is what you mentioned. And the other rule is to adjust clearance for InPolygon / InComponentClass('NetTieDirect'). Minimum clearance for that rule is set to a small amount to prevent the pulling back of copper where it shouldn't.

And thanks to you mentioning it I now know how to put polygons in draft mode.

[debassociates]

This thread is a bit old, but after struggling with net tie myself I wanted to close the loop on this.  The key to the net tie is selecting the "Type" as Net Tie (in BOM) as an another poster noted.  You'll find that option in the schematic Library Component Properties Dialog for your net tie.  Also note that Altium doesn't update this in the design using design>update.  I had to change this in the design since I had already added the net tie.

[Tobias89]

Hello,

I also wanted to use net ties. In schematic library, I chose Net Tie type, and took 0603 resistor footprint and edited it (drew a track between pads). However, the problem is that, in some moment during PCB design, that track got deleted (removed the short between pads). And at the end of design, when using Tools -> Update from PCB Libraries, Altium didn't recognize this (I included all layers in comparison)! How is that possible, is it a bug in Altium?

This is a net tie footprint:


...and this is where it got deleted (should short NetC74_2 and NetR26_2):


This is the footprint comparison result:


Does anybody know what could be the problem?

[AlfBaz]

Does anybody know what could be the problem?

I've always found updating from the library problematic unless the library was specific to the project, usually created with the create pcb library command. I normally get the results I expect by altering a footprint, saving it and then in the library editor, selecting update PCB with current footprint

[Tobias89]

Does anybody know what could be the problem?

I've always found updating from the library problematic unless the library was specific to the project, usually created with the create pcb library command. I normally get the results I expect by altering a footprint, saving it and then in the library editor, selecting update PCB with current footprint

That's what I also normally do. This was only one of the checkpoints at the end of design phase, to make sure all footprints are up to date... Until now, I haven't noticed this is unsafe method..

[prebblet]

My option for this:

Allow short circuits in the Rules
Goto -  Tools>>Preferences>>PCB editor>>Interactive Routing, and change Current mode to Ignore obstacles

Then connect your 2 tracks. Then change the preference back

It still comes up with errors but works for me.

[AshPres]

I finally got this to work.  (Using a Net Tie without any DRC or workarounds).

 I generated a Net Tie component as documented by Altium, complete with setting the component type to Net Tie.

However, I did NOT use copper (a fill, or a line) between the two pads.  Instead I made the PADS large enough to OVERLAP directly without connected copper.

I do have rules in my design that allow this component to direct connect to a plane (but that isn't necessary, it should work just running tracks or allowing a thermal relief connect).

In the schematic (as Altium details) the two pads are connected to different nets.  In the layout, the nets are connected by virtue of the pad overlap, and there are no DRC errors thrown even with the  "Verify Shorting Copper" rule enabled.

[T3sl4co1l]

Note that, when the PCB goes to fab and test, they'll complain that those two nets are shorted, and probably observe that they were shorted intentionally, but will check regardless.  I mean, if it's a PCB fab with any basic level of service, not the budget ones.

Tim

[will9twl]

what if you needed planes to net tie at an exposed pad?

well, at least that's what happened for me.

my approach may not be preferred, but i'll just share it anyway.

1. created a rule for short-circuiting the 2 nets of interest (eg. AGND and PGND)
2. at the exposed pad, put vias and have them connected to the net PGND, as an example...
3. poured polygon for AGND in G1 layer, and PGND in G2 layer
4. you'll see that at G1 layer, the AGND polygon will go around the PGND vias on the exposed pads. lovely. now put a fill over it, and have it connect to AGND. it should work fine with no DRC error as you have already created the short-circuit rule for AGND and PGND.

did it worked for you? let me know your comments