Author Topic: logic design Question: Doubling a pulse too two clock pulses / delaying by 1 clk  (Read 5219 times)

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Offline BurnedResistorTopic starter

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Hello All,

Fairly new to logic design so bear with me :). I was trying to convert a pulse of a single clk cycle image to a pulse on the next pulse, and a pulse the width of two clock pulses (see attached pic again)


I was however struggeling quite a bit.

Is this possible with a fairly easy logic design? Generating one and then generating the other from it would also work!

Regards


 

Online Ian.M

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Please use a ruler and/or squared paper so we can see how the pulse edges line up.
 

Offline capt bullshot

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You didn't specify setup and hold times - that makes it more difficult to find a suitable solution

You can do something like that:
use a D-FF latching IN at the rising edge of CLK to generate OUT1, then another D-FF latching IN or OUT1 at the falling edge of CLK to generate an intermediate signal, then push OUT1 and intermediate into an AND gate to generate OUT2

Edit: OUT2 could also be generated by AND-ing OUT1 with inverted CLK - beware of glitches

« Last Edit: April 26, 2017, 09:29:02 am by capt bullshot »
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Offline BurnedResistorTopic starter

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Please use a ruler and/or squared paper so we can see how the pulse edges line up.
You didn't specify setup and hold times - that makes it more difficult to find a suitable solution

You can do something like that:
use a D-FF latching IN at the rising edge of CLK to generate OUT1, then another D-FF latching IN or OUT1 at the falling edge of CLK to generate an intermediate signal, then push OUT1 and intermediate into an AND gate to generate OUT2

Edit: OUT2 could also be generated by AND-ing OUT1 with inverted CLK - beware of glitches

Very Nice!

Thank you for your help, and sorry about the diagram. For the second round I figure out WaveDrom :)

Now the previous circuit descried by capt bulshot required the signal to be present before the clock, if they are in the same instant, there is a race condition. Is it possible to design a circuit which would perform similarly, but even if the input came up after the beginning of the clock pulse?

Kinda hard to explain, diagram should talk novels (hopefully!)

« Last Edit: April 26, 2017, 10:52:15 am by BurnedResistor »
 

Offline capt bullshot

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Well - it still depends on the timing of IN related to CLK:

you may consider using a D-FF with Set/Reset inputs like the '74:
Set the FF via the static S input, using inverted IN, use the rising edge of CLK to latch a static LOW (reset at CLK edge) - maybe you want to add some CLK enable logic (like AND of (FF out latched with second D-FF at the falling edge of CLK) and CLK) to avoid too early resetting.
« Last Edit: April 26, 2017, 11:10:43 am by capt bullshot »
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Offline BurnedResistorTopic starter

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Ups. Now with white background!
 

Offline BrianHG

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The simplest is using a DFF, tie the DFF's data input to GND.  The DFF's positive edge clk to your 'clk'.  Positive asynchronous set to your 'in'.

When your 'in' goes high, the DFF's output goes high immediately and locks high until your 'in' goes low.  The output of the DFF wont go low until the next 'clk' transition from low to high.

You didn't provide the exact timing for out #2.  There are similar tricks to do that signal as well depending on how you want it timed.
Since I don't know what king of IC you may have access to, the appropriate 2 or 3 74LSxx, or 74HCxx should work, though I was personally thinking PAL/GAL/FPGA code with my above instructions since you placed the question in this section.

A single positive edge triggered DFF register with async set written in Verilog should be around 5 lines of code.

It's time for bed, I hope I got this right...


« Last Edit: April 26, 2017, 11:57:43 am by BrianHG »
 

Offline Rerouter

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So to my eyes, you want Out to Equal In while it is high, and then remain high until the next rising edge,

Equally you want output 2 to be the XNOR of Out and In. (Only high when they are different, probably done with 2 nand gates)

Attached looks to meet your timing diagram, uses a hex nand gate chip.
 

Offline hamster_nz

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Would something like https://www.onsemi.com/pub/Collateral/MC74HC74A-D.PDF be of any help? It is a D Flipflop with async set /reset.

You would need to tie D low, invert your input to match the 'inverted set' input, and it will stretch any incoming pulse till the next clock edge.
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Offline rstofer

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Would something like https://www.onsemi.com/pub/Collateral/MC74HC74A-D.PDF be of any help? It is a D Flipflop with async set /reset.

You would need to tie D low, invert your input to match the 'inverted set' input, and it will stretch any incoming pulse till the next clock edge.

I never really liked asynchronous logic. The input pulse is apparently unrelated to the clock and it could turn out that the input bit sets the flop a couple of nanoseconds before the falling edge of the clock resets it.  Runt pulses seem guaranteed.
« Last Edit: April 27, 2017, 11:02:14 pm by rstofer »
 

Offline BrianHG

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I never really liked asynchronous logic. The input pulse is apparently unrelated to the clock and it could turn out that the input bit sets the flop a couple of nanoseconds before the falling edge of the clock resets it.  Runt pulses seem guaranteed.
In my first description, I chosen this solution since the OT didn't define setup times, delays, and other important info if you want to make a clean RTL design.  Remembering that this question was placed in the FPGA/Microcontroller forum, I think the OT was looking for logic code to put in a FPGA or PLD.

If I were to do a cleaner version of something along the line of interpreting the OT's inputs, I would use 2 D-flipflops in a row, DQ-DQ, with positive and negative edge triggered clock input shifting the input at every clock transition.  This would be clean and no async.

Data in would come from the OP's data in.
Out would be DFF's #1, #2 output OR ed together.

No async here, the input is just being shifted every rise and fall of the clock, unless you have a really old PLD/FPGA from years back which couldn't do positive and negative clocking on a macrocell.

BUT, looking at the OT's second diagram, his output swings immediately after the source rises, exactly 50% in-between a clock cycle.
I guess you can cut my design down to 1 D-FF and OR the input with the output of DFF's for the effect.

Without knowing why and how the OP needs this pattern, what it is being used for, this is the best suggestion I can make.

However, the best FPGA solution is to do all logic on a single rising edge, synchronous clock design if possible.  All all IOs, especially if high speed, are synchronous DFF driven or data inputted unless you are struggling to preserve macrocells.

The last solution is just to use a enable low transparent latch (tied to clk).  When the !LE input his high, the output = the input (in) in real time, but, when the !LE goes low, the output holds the last state.  This might be finicky due to the timing of the OP's source waveforms.
« Last Edit: April 28, 2017, 12:10:57 pm by BrianHG »
 

Offline rstofer

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In my first description, I chosen this solution since the OT didn't define setup times, delays, and other important info if you want to make a clean RTL design.  Remembering that this question was placed in the FPGA/Microcontroller forum, I think the OT was looking for logic code to put in a FPGA or PLD.
I don't think FPGAs like asynchronous logic.  I know Xilinx ISE warns about it.
Quote

If I were to do a cleaner version of something along the line of interpreting the OT's inputs, I would use 2 D-flipflops in a row, DQ-DQ, with positive and negative edge triggered clock input shifting the input at every clock transition.  This would be clean and no async.

Data in would come from the OP's data in.
Out would be DFF's #1, #2 output OR ed together.

No async here, the input is just being shifted every rise and fall of the clock, unless you have a really old PLD/FPGA from years back which couldn't do positive and negative clocking on a macrocell.
I was thinking, broadly, about doubling the clock rate.  Personally, I have never tried clocking on both edges but it serves the same purpose.
Quote

BUT, looking at the OT's second diagram, his output swings immediately after the source rises, exactly 50% in-between a clock cycle.
I guess you can cut my design down to 1 D-FF and OR the input with the output of DFF's for the effect.
I was wondering about the timing and why the input is so far removed from the clock edges and the pulse so much narrower than a clock state.  I wasn't sure that 50% was real or just where the OP happened to draw the input.

It seems to me that the alignment of the leading edge is important somehow but the trailing edge is also a concern.  Is the pulse always about 1/4 of a clock state.  Will the falling edge of the input always occur before the falling edge of the clock?  I guess we take the diagram as is...

Quote
Without knowing why and how the OP needs this pattern, what it is being used for, this is the best suggestion I can make.

However, the best FPGA solution is to do all logic on a single rising edge, synchronous clock design if possible.  All all IOs, especially if high speed, are synchronous DFF driven or data inputted unless you are struggling to preserve macrocells.

The last solution is just to use a enable low transparent latch (tied to clk).  When the !LE input his high, the output = the input (in) in real time, but, when the !LE goes low, the output holds the last state.  This might be finicky due to the timing of the OP's source waveforms.
Yup!  Single rising edge is what I prefer.  Even if I have to create a 2x clock (assuming I get to choose the clock).
 

Offline Someone

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In my first description, I chosen this solution since the OT didn't define setup times, delays, and other important info if you want to make a clean RTL design.  Remembering that this question was placed in the FPGA/Microcontroller forum, I think the OT was looking for logic code to put in a FPGA or PLD.
I don't think FPGAs like asynchronous logic.  I know Xilinx ISE warns about it.
They warn about it as they can't make timing constraints against asynchronous designs, but the FPGA fabric actually has quite a few asynchronous primitives and the capability to do dirty tricks if you want.
 

Offline hamster_nz

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Just in case BurnedResistor is still watching, and is thinking FPGA/CPLD, here is some code that seems to do what he is after:
Code: [Select]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test_module is
    Port ( clk : in STD_LOGIC;
           i : in STD_LOGIC;
           q1 : out STD_LOGIC;
           q2 : out STD_LOGIC);
end test_module;

architecture Behavioral of test_module is
    signal reg0 : std_logic := '0';
    signal reg1 : std_logic := '0';
begin
    q1 <= reg0;
    q2 <= reg1;
   
process(clk,i)
    begin
        if i = '1' then
            reg0 <= '1';
            reg1 <= '1';
        elsif rising_edge(clk) then
            reg1 <= reg0;
            reg0 <= '0';
        end if;
    end process;

end Behavioral;

You can see a video of it running on a devboard here:



(LED0 is the clock, LED1 is Q1, LED2 is Q2, and the button is the input I)

I've also attached a schematic.
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Offline sokoloff

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@hamster_nz - that video comes up as unavailable for me. (might be set to private for you?)
 
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Offline hamster_nz

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@hamster_nz - that video comes up as unavailable for me. (might be set to private for you?)

Oops, grrrrr, sigh.. fixed
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