Translate 3V SPI to 5V SPI

[ggchab]

I am testing that circuit to control SPI chips (MCP4921 and MCP41100) powered in 5V while the micro-controller (a PIC24) is powered in 3V (VCC). I added the diode D1 because the 5V power supply is often switched off to save battery energy.

I don't clearly understand why I still read about 1V on SPI_SCK_5V when SPI_SCK is at 3V and the 5V supply is disconnected. (in fact, I apply a 3V 200KHz square wave on SPI_SCK). For my test circuit, nothing else than my scope probe is connected to SPI_SCK_5V. Could it be some kind of capacitive coupling through the diode? Could the voltage on SPI_SCK_5V (and other SPI lines: SI, CS) damage the chips when they are not powered ? Thank you

[salbayeng]

OK
This is just a spurious reading you have due to the high impedance of your scope.
Schottky diodes have this annoying feature "leakage current" , and the letters and numbers after the main partnumber can be  very different parts. Lucky you didn't use the BAT60A !

If I look up the ST  BAT60J datasheet , and check the leakage current, with 5v , at 25C its 1uA typ (4uA max) , at 80C it shoots up to 73uA
The leakage current doesn't vary much with voltage (at the lower voltages) , so for example if you had 3v on SPI_SCK, this would drop to 2.5v on the drain of T1 (due to body diode) , if I then leak 1uA from this 2.5v , I will get ~ 1v across the scope probe of 1MegOhm (on +5v or SPI_SCK_5v)  , which is about what you see, so nothing unexpected there.
It shouldn't create any issues in your project unless you have some nanopower logic that is still hanging in there at 1v, there's a slim chance it may not reset as it doesn't see zero volts. It certainly won't damage anything.
If it bothers you just put a 100k resistor to ground on the +5v rail, although this may not be necessary once you put some real parts in your project , hanging off the 5v rail.

The theoretical solution would be to put another BSS138 back to back with the existing one ,  so SPI_CLK goes to drain of new BSS138, the source connects to source of T1, and the gates are tied together.  This will shift the switching threshold slightly, but would produce a lower "zero" voltage on SPI_SCK_5v as you can omit D1  and that would need to be checked. Personally I wouldn't bother with this. (google "back to back mosfet" and look at the images).

Schottky diodes need to be used with caution in battery powered projects, pick the wrong one in a power supply , and it will leak 10's of mA's on a hot day - bad news for any battery!.

[ggchab]

Thank you for your answer and useful information about Schottky diodes. Glad I can keep the circuit as it is without too many concern.

[tatus1969]

isn't the PIC 5V tolerant? If yes, then the solution can be much simpler. To interface a signal from slave to PIC, just connect it. To interface from PIC to slave, use a resistive divider. Make the impedance of that low enough so that it does not limit your desired clock rate.

[ggchab]

The problem is that the PIC is working in 3V and generates the SCK, SI and CS SPI signals. High level might be too low for the 5V chips. And also, the chips should be "disconnected" from the SPI bus when they are not powered.

[tatus1969]

The problem is that the PIC is working in 3V and generates the SCK, SI and CS SPI signals. High level might be too low for the 5V chips. And also, the chips should be "disconnected" from the SPI bus when they are not powered.

Can the PIC run its SPI outputs in open drain mode? If yes, then the 5V supplied pull-up is still in.

[ggchab]

I did not known SPI could use open collector lines. But I forgot to say that I also have other SPI chips (sram, humidity and temperature sensor) powered in 3V. Those chips are always powered while the 5V ones are not (to save battery).

[T3sl4co1l]

You might use a bus interface chip, like a 74LVC or 74AUP something or other.

In particular, the 74LVCT family has TTL/LVCMOS compatible input thresholds, and 5V tolerant inputs.  This means the inputs will respond to 3.3V CMOS signals, while the 5V VDD supply can be powered off and it won't be parasite-powered through protection diodes.  (For protection, the pins have zener diodes to ground, not clamp diodes to VDD and GND.)

Tim

[ggchab]

Thank you for the information. 74AUP chips are interesting but they do not seem to accept a supply voltage higher than 3.6V or am I wrong ? Until now, I could not find any details on 74LVCT chips. I also looked on Farnell or Digikey sites but without success.

[T3sl4co1l]

Oops, more like LVT:
http://www.digikey.com/product-detail/en/nxp-usa-inc/74LVT125PW,118/568-2311-1-ND/946771

Anyway, search around, stuff like that exists!

Tim

[ggchab]

Many thanks. I found the 74AHCT1G125 that seems to be doing exactly what I need 

[FrankBuss]

There are special voltage level shifter ICs like the SN74LVC8T245 (8 bit) or the SN74LVC1T45 (1 bit) which work great for such applications.

[ggchab]

Thank you. That's also a very good option !

So, I can have the 3V supply on VCCA and the 5V on VCCB. The would use A-port to B-port direction. If I switch off the 5V and still have the 3V SPI signal on the A pin, this should not damage the ship and B-port output should be disabled. Is it correct ?

I have a similar question for the 74AHCT1G125. If I switch off the 5V and still have the 3V SPI signal on the A pin, will it parasite-power or damage the chip ? What will happen on the output pin ? If possible, I would like to know before ordering the chips. Thank you.

[FrankBuss]

So, I can have the 3V supply on VCCA and the 5V on VCCB. The would use A-port to B-port direction. If I switch off the 5V and still have the 3V SPI signal on the A pin, this should not damage the ship and B-port output should be disabled. Is it correct ?

I've never used it for such an application, but the datasheet says "The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.". So a high load resistor on the 5V line to GND should do it, if you don't have already another load which takes it down to GND, if there is no 5V supply.

[ggchab]

OK, this is most probably the chip I need for my application. Thank you.

[Ian.M]

It depends.  If all your SPI slave devices use 5V levels, then any of the 5V capable non-inverting dual Vcc level shifters will be fine (but beware of limitations on which VCC can be higher), but if you have a mix of 5V and 3.3V logic level devices on the bus then all devices that use different levels to the master will need a tristatable level shifting buffer on MISO, controlled by the /SS signal to that device.  As you are going from 5V to 3.3V for that signal you can simply use a 3.3V tristate buffer with a 5V toerant input.

Going the other way, from 3.3V to 5V, with a switched 5V power domain you have to check individual device datasheets to see if they can tolerate Vin when powered down.  Be careful of substituting similar part numbers from other manufacturers without checking the powerdown behaviour in the datasheet.

[ggchab]

Yes, I'll have a mix of 5V and 3V devices. But the ones on the 5V supply will not use MISO even if I don't understand while that line would need a tristable level shifting buffer.
I don't understand what you mean by "if device can tolerate Vin when powered down". I am simply planning to use the enable pin of the voltage regulator to shutdown the 5V supply and the connected devices (and VCCB of the 74LVC1T45). Is it incorrect ?

[Ian.M]

The 74LVC1T45 specifically supports operation with one or both Vcc supplies powered down and its I/O pins are hi-Z while its in that state.

MISO (Master in slave out) of slave devices *MUST* be tristated when the slave's /SS signal is high, otherwise you cant have multiple devices on the SPI bus with separate /SS signals due to bus conflicts.   Therefore if you have any 3.3V slaves, the MISO level converter output must be tristated whenever no 5V device /SS line is active.  The easiest way to do this is to use a separate tristatable level converter for each 5V slave and use each slave's /SS signal to control its MISO level converter.  However if the *ONLY* 3.3V device is the master you can simply use one 74LVC1T45 for all the 5V MISO signals bussed together, without tristate capability, as there is nothing else on the 3.3V side it can conflict with.   

[ggchab]

Many thanks for the additional information. I did not think to the conflict problem.

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